On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote:

The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size.

Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks.

Cc: stable@vger.kernel.org # 5.17 Fixes: 9ac8999e8d6c ("arm64: dts: qcom: sm8350: Add LLCC node") Reported-by: Parikshit Pareek quic_ppareek@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

---

arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..7f76778e1bc8 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc";

• 	reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
  

• 	reg-names = "llcc_base", "llcc_broadcast_base";
  

• 	reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
  

• 	      <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
  

• 	      <0 0x09600000 0 0x58000>;
  

  };

usb_1: usb@a6f8800 {

Reviewed-by: Sai Prakash Ranjan quic_saipraka@quicinc.com