Hi,
This series fixes the UFS resume from suspend issue by marking the UFS PHY GDSCs as ALWAYS_ON. Starting from SM8550, UFS PHY GDSCs doesn't support retention state. So we should keep them always on so that they don't loose the state during suspend.
Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org --- Manivannan Sadhasivam (2): clk: qcom: gcc-sm8550: Keep UFS PHY GDSCs ALWAYS_ON clk: qcom: gcc-sm8650: Keep UFS PHY GDSCs ALWAYS_ON
drivers/clk/qcom/gcc-sm8550.c | 4 ++-- drivers/clk/qcom/gcc-sm8650.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) --- base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc change-id: 20241107-ufs-clk-fix-e49ee2097594
Best regards,
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
Starting from SM8550, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to below UFS error during resume as observed on SM8550-QRD:
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: 1fe8273c8d40 ("clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag") Reported-by: Neil Armstrong neil.armstrong@linaro.org Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org --- drivers/clk/qcom/gcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 5abaeddd6afc..7dd08e175820 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3046,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc ufs_mem_phy_gdsc = { @@ -3055,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc usb30_prim_gdsc = {
On 07/11/2024 12:58, Manivannan Sadhasivam via B4 Relay wrote:
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
Starting from SM8550, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to below UFS error during resume as observed on SM8550-QRD:
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: 1fe8273c8d40 ("clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag") Reported-by: Neil Armstrong neil.armstrong@linaro.org Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
drivers/clk/qcom/gcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 5abaeddd6afc..7dd08e175820 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3046,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc ufs_mem_phy_gdsc = { @@ -3055,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc usb30_prim_gdsc = {
Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8550-QRD Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8550-HDK
Thanks, Neil
On Thu, Nov 07, 2024 at 11:58:09AM +0000, Manivannan Sadhasivam via B4 Relay wrote:
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
Starting from SM8550, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to below UFS error during resume as observed on SM8550-QRD:
Unless I'm mistaken, ALWAYS_ON makes GDSC keep the gendpd ALWAYS_ON as well, which in turn would ensure that any parent power-domain is kept active - which in the case of GCC would imply CX.
The way we've dealt with this elsewhere is to use the PWRSTS_RET_ON flag in pwrsts; we then keep the GDSC active, but release any votes to the parent and rely on hardware to kick in MX when we're shutting down CX. Perhaps this can't be done for some reason?
PS. In contrast to other platforms where we've dealt with issues of under voltage crashes, I see &gcc in sm8550.dtsi doesn't specify a parent power-domain, which would mean that the required-opps = <&nom> of &ufs_mem_hc is voting for nothing.
Regards, Bjorn
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: 1fe8273c8d40 ("clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag") Reported-by: Neil Armstrong neil.armstrong@linaro.org Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
drivers/clk/qcom/gcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 5abaeddd6afc..7dd08e175820 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3046,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON,
}; static struct gdsc ufs_mem_phy_gdsc = { @@ -3055,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON,
}; static struct gdsc usb30_prim_gdsc = {
-- 2.25.1
On Tue, Nov 26, 2024 at 10:21:10PM -0600, Bjorn Andersson wrote:
On Thu, Nov 07, 2024 at 11:58:09AM +0000, Manivannan Sadhasivam via B4 Relay wrote:
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
Starting from SM8550, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to below UFS error during resume as observed on SM8550-QRD:
Unless I'm mistaken, ALWAYS_ON makes GDSC keep the gendpd ALWAYS_ON as well, which in turn would ensure that any parent power-domain is kept active - which in the case of GCC would imply CX.
That's correct. But there is one more way to fix this issue. We can powerdown UFS (controller and device) during suspend and the ufs-qcom driver can specify the default suspend level based on platform. I think that would be more appropriate than forbidding CX power collapse for the whole SoC.
Let me cook up a patch.
The way we've dealt with this elsewhere is to use the PWRSTS_RET_ON flag in pwrsts; we then keep the GDSC active, but release any votes to the parent and rely on hardware to kick in MX when we're shutting down CX. Perhaps this can't be done for some reason?
UFS team told me that there is no 'hardware retention' for UFS PHYs starting from SM8550 and asked to keep GDSCs ALWAYS_ON. So that would mean, there is no MX backing also.
- Mani
PS. In contrast to other platforms where we've dealt with issues of under voltage crashes, I see &gcc in sm8550.dtsi doesn't specify a parent power-domain, which would mean that the required-opps = <&nom> of &ufs_mem_hc is voting for nothing.
Regards, Bjorn
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: 1fe8273c8d40 ("clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag") Reported-by: Neil Armstrong neil.armstrong@linaro.org Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
drivers/clk/qcom/gcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 5abaeddd6afc..7dd08e175820 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3046,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON,
}; static struct gdsc ufs_mem_phy_gdsc = { @@ -3055,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON,
}; static struct gdsc usb30_prim_gdsc = {
-- 2.25.1
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
In SM8650, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to UFS error similar to below during resume:
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org --- drivers/clk/qcom/gcc-sm8650.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index fd9d6544bdd5..ddc38caf7160 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3480,7 +3480,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc ufs_mem_phy_gdsc = { @@ -3489,7 +3489,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc usb30_prim_gdsc = {
On 07/11/2024 12:58, Manivannan Sadhasivam via B4 Relay wrote:
From: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
In SM8650, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to UFS error similar to below during resume:
ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5
Cc: stable@vger.kernel.org # 6.8 Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") Suggested-by: Nitin Rawat quic_nitirawa@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
drivers/clk/qcom/gcc-sm8650.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index fd9d6544bdd5..ddc38caf7160 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3480,7 +3480,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc ufs_mem_phy_gdsc = { @@ -3489,7 +3489,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
- .flags = POLL_CFG_GDSCR | ALWAYS_ON, };
static struct gdsc usb30_prim_gdsc = {
Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8650-QRD Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8650-HDK
Thanks! Neil
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Bjorn Andersson -
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Neil Armstrong