This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
Anshuman Khandual (7): arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
Documentation/arch/arm64/booting.rst | 22 ++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++ arch/arm64/tools/sysreg | 103 +++++++++++++++++++++++++++ 3 files changed, 150 insertions(+)
This updates ID_AA64MMFR0_EL1 register fields as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-2-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit cc15f548cc77574bcd68425ae01a796659bd3705] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b081b54d6d22..a6cbe0dcd63b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1591,6 +1591,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1652,6 +1653,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: cc15f548cc77574bcd68425ae01a796659bd3705
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: cc15f548cc775 ! 1: 0ac931bb8341b arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-2-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit cc15f548cc77574bcd68425ae01a796659bd3705] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## @@ arch/arm64/tools/sysreg: EndEnum ---
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.13.y | Success | Success |
This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-3-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 44844551670cff70a8aa5c1cde27ad1e0367e009] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a6cbe0dcd63b..9ce8602dd40f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2546,6 +2546,35 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg
+Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 2/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: 44844551670cff70a8aa5c1cde27ad1e0367e009
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: 44844551670cf ! 1: fdda1b4072c20 arm64/sysreg: Add register fields for HDFGRTR2_EL2 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-3-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit 44844551670cff70a8aa5c1cde27ad1e0367e009] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## -@@ arch/arm64/tools/sysreg: Field 0 E0HTRE +@@ arch/arm64/tools/sysreg: Field 1 ICIALLU + Field 0 ICIALLUIS EndSysreg
- +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-4-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 2f1f62a1257b9d5eb98a8e161ea7d11f1678f7ad] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9ce8602dd40f..f5a1fa75ec72 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2575,6 +2575,34 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg
+Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 3/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: 2f1f62a1257b9d5eb98a8e161ea7d11f1678f7ad
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: 2f1f62a1257b9 ! 1: 8cf4af8e4f698 arm64/sysreg: Add register fields for HDFGWTR2_EL2 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-4-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit 2f1f62a1257b9d5eb98a8e161ea7d11f1678f7ad] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## @@ arch/arm64/tools/sysreg: Field 1 nPMIAR_EL1 ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
This adds register fields for HFGITR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-5-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 9401476f17747586a8bfb29abfdf5ade7a8bceef] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f5a1fa75ec72..088e3be8f884 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2775,6 +2775,12 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg
+Sysreg HFGITR2_EL2 3 4 3 1 7 +Res0 63:2 +Field 1 nDCCIVAPS +Field 0 TSBCSYNC +EndSysreg + Sysreg ZCR_EL2 3 4 1 2 0 Fields ZCR_ELx EndSysreg
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 4/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: 9401476f17747586a8bfb29abfdf5ade7a8bceef
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: 9401476f17747 ! 1: 890c5150d605f arm64/sysreg: Add register fields for HFGITR2_EL2 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-5-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit 9401476f17747586a8bfb29abfdf5ade7a8bceef] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## @@ arch/arm64/tools/sysreg: Field 1 AMEVCNTR00_EL0 ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
This adds register fields for HFGRTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-6-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 59236089ad5243377b6905d78e39ba4183dc35f5] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 088e3be8f884..0875e0057706 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2603,6 +2603,25 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg
+Sysreg HFGRTR2_EL2 3 4 3 1 2 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Field 1 nERXGSR_EL1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 5/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: 59236089ad5243377b6905d78e39ba4183dc35f5
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: 59236089ad524 ! 1: 84378bfa5e060 arm64/sysreg: Add register fields for HFGRTR2_EL2 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-6-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit 59236089ad5243377b6905d78e39ba4183dc35f5] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## @@ arch/arm64/tools/sysreg: Field 1 nPMIAR_EL1 ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
This adds register fields for HFGWTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-7-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit ea37be0773f04420515b8db49e50abedbaa97e23] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0875e0057706..268f1b808e3f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2622,6 +2622,25 @@ Field 1 nERXGSR_EL1 Field 0 nPFAR_EL1 EndSysreg
+Sysreg HFGWTR2_EL2 3 4 3 1 3 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Res0 1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 6/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: ea37be0773f04420515b8db49e50abedbaa97e23
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: ea37be0773f04 ! 1: ccc9b1721d196 arm64/sysreg: Add register fields for HFGWTR2_EL2 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-7-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit ea37be0773f04420515b8db49e50abedbaa97e23] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm64/tools/sysreg ## @@ arch/arm64/tools/sysreg: Field 1 nERXGSR_EL1 ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 access from EL1 requires appropriate EL2 fine grained trap configuration via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2. Otherwise such register accesses will result in traps into EL2.
Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers.
Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2 based registers to be accessible in EL2.
Cc: Will Deacon will@kernel.org Cc: Mark Rutland mark.rutland@arm.com Cc: Rob Herring robh@kernel.org Cc: Jonathan Corbet corbet@lwn.net Cc: Marc Zyngier maz@kernel.org Cc: Oliver Upton oliver.upton@linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Fixes: 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control") Fixes: d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") Tested-by: Rob Herring (Arm) robh@kernel.org Reviewed-by: Rob Herring (Arm) robh@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250227035119.2025171-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 858c7bfcb35e1100b58bb63c9f562d86e09418d9] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+)
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index 3278fb4bf219..ee4dca2ddfb6 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
+ For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
- If EL3 is present and the kernel is entered at EL2: @@ -382,6 +388,22 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
+ For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9): + + - If EL3 is present: + + - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + + - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
- If the kernel is entered at EL1 and EL2 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 4ef52d7245bb..9e44c13711e5 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -233,6 +233,30 @@ .Lskip_fgt_@: .endm
+.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_@ + + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 + b.lt .Lskip_pmuv3p9_@ + + orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 +.Lskip_pmuv3p9_@: + msr_s SYS_HDFGRTR2_EL2, x0 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HFGRTR2_EL2, xzr + msr_s SYS_HFGWTR2_EL2, xzr + msr_s SYS_HFGITR2_EL2, xzr +.Lskip_fgt2_@: +.endm + .macro __init_el2_gcs mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 @@ -283,6 +307,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 __init_el2_gcs .endm
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ℹ️ This is part 7/7 of a series ⚠️ Found matching upstream commit but patch is missing proper reference to it
Found matching upstream commit: 858c7bfcb35e1100b58bb63c9f562d86e09418d9
Status in newer kernel trees: 6.14.y | Not found
Note: The patch differs from the upstream commit: --- 1: 858c7bfcb35e1 ! 1: 5a56cf2361642 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 @@ Commit message Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250227035119.2025171-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com + [cherry picked from commit 858c7bfcb35e1100b58bb63c9f562d86e09418d9] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## Documentation/arch/arm64/booting.rst ## @@ Documentation/arch/arm64/booting.rst: Before jumping into the kernel, the following conditions must be met: ---
NOTE: These results are for this patch alone. Full series testing will be performed when all parts are received.
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.14.y | Success | Success |
On Tue, Apr 08, 2025 at 03:08:52PM +0530, Anshuman Khandual wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
But you aren't going to fix the 6.14.y tree? We can't take patches that skip newer stable releases for obvious reasons.
And 6.13.y is only going to be alive for a few more days, is there some specific reason this is needed now for 6.13.y?
thanks,
greg k-h
On 4/8/25 15:23, Greg KH wrote:
On Tue, Apr 08, 2025 at 03:08:52PM +0530, Anshuman Khandual wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
But you aren't going to fix the 6.14.y tree? We can't take patches that skip newer stable releases for obvious reasons.
And 6.13.y is only going to be alive for a few more days, is there some specific reason this is needed now for 6.13.y?
I have also sent same series for 6.14 stable version as well. It will be great to have these patches applied both on 6.13 as well 6.14. Thank you.
On Tue, Apr 08, 2025 at 03:34:51PM +0530, Anshuman Khandual wrote:
On 4/8/25 15:23, Greg KH wrote:
On Tue, Apr 08, 2025 at 03:08:52PM +0530, Anshuman Khandual wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
But you aren't going to fix the 6.14.y tree? We can't take patches that skip newer stable releases for obvious reasons.
And 6.13.y is only going to be alive for a few more days, is there some specific reason this is needed now for 6.13.y?
I have also sent same series for 6.14 stable version as well. It will be great to have these patches applied both on 6.13 as well 6.14. Thank you.
TBH, 6.13 is end of life soon, so not sure it's worth carrying those patches. Do you have a reason for this Anshuman?
On 4/8/25 21:57, Catalin Marinas wrote:
On Tue, Apr 08, 2025 at 03:34:51PM +0530, Anshuman Khandual wrote:
On 4/8/25 15:23, Greg KH wrote:
On Tue, Apr 08, 2025 at 03:08:52PM +0530, Anshuman Khandual wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
But you aren't going to fix the 6.14.y tree? We can't take patches that skip newer stable releases for obvious reasons.
And 6.13.y is only going to be alive for a few more days, is there some specific reason this is needed now for 6.13.y?
I have also sent same series for 6.14 stable version as well. It will be great to have these patches applied both on 6.13 as well 6.14. Thank you.
TBH, 6.13 is end of life soon, so not sure it's worth carrying those patches. Do you have a reason for this Anshuman?
Not particularly for 6.13.
We can just skip these from 6.13 if that is not going to be around for long. I was under the impression that all maintained stable releases starting from where this problem got introduced upto now, need to be covered for this back porting.
On Tue, Apr 8, 2025 at 4:39 AM Anshuman Khandual anshuman.khandual@arm.com wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter")
This landed in v6.12, not 6.13. As 6.12 is LTS, it needs the backport.
0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
Anshuman Khandual (7): arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
Documentation/arch/arm64/booting.rst | 22 ++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++ arch/arm64/tools/sysreg | 103 +++++++++++++++++++++++++++ 3 files changed, 150 insertions(+)
-- 2.30.2
On 4/8/25 23:10, Rob Herring wrote:
On Tue, Apr 8, 2025 at 4:39 AM Anshuman Khandual anshuman.khandual@arm.com wrote:
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.13 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter")
This landed in v6.12, not 6.13. As 6.12 is LTS, it needs the backport.
You are right, missed that. I will send this series for 6.12 stable as well.
BTW also need to backport the following commit for ID_AA64DFR0_EL1_PMUVer_V3P9 symbol which is required in __init_el2_fgt2(). Because this commit is not part of the current v6.12 stable tree.
a40e1ec92e46 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
Anshuman Khandual (7): arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
Documentation/arch/arm64/booting.rst | 22 ++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++ arch/arm64/tools/sysreg | 103 +++++++++++++++++++++++++++ 3 files changed, 150 insertions(+)
-- 2.30.2
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