GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe but it needs to be programmed for both.
Program both pipes in hw_init and introducea separate reglist for it in order to add this register to the dynamic reglist which supports restoring registers per pipe.
Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Signed-off-by: Anna Maniscalco anna.maniscalco2000@gmail.com --- Changes in v2: - Added missing Cc: stable to commit - Added pipe_regs to all 7xx gens - Null check pipe_regs in a7xx_patch_pwrup_reglist - Added parentheses around bitwise and in a7xx_patch_pwrup_reglist - Use A7XX_PIPE_{BR, BV, NONE} enum values - Link to v1: https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail.... --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++++++++++ 4 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 29107b362346..10732062d681 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A6XX_RB_NC_MODE_CNTL, REG_A6XX_RB_CMP_DBG_ECO_CNTL, - REG_A7XX_GRAS_NC_MODE_CNTL, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, REG_A6XX_UCHE_GBIF_GX_CONFIG, REG_A6XX_UCHE_CLIENT_PF, @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = {
DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
+static const struct adreno_reglist_pipe a7xx_reglist_pipe_regs[] = { + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, +}; + +DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_reglist_pipe); + static const struct adreno_info a7xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x07000200), @@ -1491,6 +1496,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a730_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, + .pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020000, }, @@ -1513,6 +1519,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, + .pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202, @@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist, + .pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7050001, .gmu_cgc_mode = 0x00020202, @@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist, + .pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202, @@ -1623,6 +1632,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, + .pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x70f0000, .gmu_cgc_mode = 0x00020222, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0200a7e71cdf..422ce4c97f70 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode);
- if (adreno_is_a7xx(adreno_gpu)) - gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, - FIELD_PREP(GENMASK(8, 5), hbb_lo)); + if (adreno_is_a7xx(adreno_gpu)) { + for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); + gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, + FIELD_PREP(GENMASK(8, 5), hbb_lo)); + } + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); + }
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len_64b << 23 | hbb_lo << 21); @@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); const struct adreno_reglist_list *reglist; + const struct adreno_reglist_pipe_list *pipe_reglist; void *ptr = a6xx_gpu->pwrup_reglist_ptr; struct cpu_gpu_lock *lock = ptr; u32 *dest = (u32 *)&lock->regs[0]; + u32 pipe_reglist_count = 0; int i;
lock->gpu_req = lock->cpu_req = lock->turn = 0; @@ -907,7 +916,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) * (<aperture, shifted 12 bits> <address> <data>), and the length is * stored as number for triplets in dynamic_list_len. */ - lock->dynamic_list_len = 0; + pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist; + if (pipe_reglist) { + for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); + for (i = 0; i < pipe_reglist->count; i++) { + if ((pipe_reglist->regs[i].pipe & BIT(pipe_id)) == 0) + continue; + *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id); + *dest++ = pipe_reglist->regs[i].offset; + *dest++ = gpu_read(gpu, pipe_reglist->regs[i].offset); + pipe_reglist_count++; + } + } + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); + } + lock->dynamic_list_len = pipe_reglist_count; }
static int a7xx_preempt_start(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 6820216ec5fc..0a1d6acbc638 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,7 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist; + const struct adreno_reglist_pipe_list *pipe_reglist; const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; u32 max_slices; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0f8d3de97636..1d0145f8b3ec 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \ .count = ARRAY_SIZE(name ## _regs), \ };
+struct adreno_reglist_pipe_list { + /** @reg: List of register **/ + const struct adreno_reglist_pipe *regs; + /** @count: Number of registers in the list **/ + u32 count; +}; + +#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ +static const struct adreno_reglist_pipe_list name = { \ + .regs = name ## _regs, \ + .count = ARRAY_SIZE(name ## _regs), \ +}; + struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info;
--- base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 change-id: 20251126-gras_nc_mode_fix-7224ee506a39
Best regards,
Hi Anna,
kernel test robot noticed the following build errors:
[auto build test ERROR on 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530]
url: https://github.com/intel-lab-lkp/linux/commits/Anna-Maniscalco/drm-msm-Fix-a... base: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 patch link: https://lore.kernel.org/r/20251128-gras_nc_mode_fix-v2-1-634cda7b810f%40gmai... patch subject: [PATCH v2] drm/msm: Fix a7xx per pipe register programming config: um-randconfig-002-20251130 (https://download.01.org/0day-ci/archive/20251130/202511301514.t3OSLc6E-lkp@i...) compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251130/202511301514.t3OSLc6E-lkp@i...)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202511301514.t3OSLc6E-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a6xx_set_ubwc_config':
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:36: error: 'A7XX_PIPE_BR' undeclared (first use in this function)
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^~~~~~~~~~~~ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:36: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:61: error: 'A7XX_PIPE_BV' undeclared (first use in this function)
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^~~~~~~~~~~~
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:860:59: error: 'A7XX_PIPE_NONE' undeclared (first use in this function); did you mean 'MSM_PIPE_NONE'?
860 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); | ^~~~~~~~~~~~~~ | MSM_PIPE_NONE drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a7xx_patch_pwrup_reglist': drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:36: error: 'A7XX_PIPE_BR' undeclared (first use in this function) 921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^~~~~~~~~~~~ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:61: error: 'A7XX_PIPE_BV' undeclared (first use in this function) 921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^~~~~~~~~~~~ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:934:59: error: 'A7XX_PIPE_NONE' undeclared (first use in this function); did you mean 'MSM_PIPE_NONE'? 934 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); | ^~~~~~~~~~~~~~ | MSM_PIPE_NONE
vim +/A7XX_PIPE_BR +853 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
807 808 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 809 { 810 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 811 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; 812 /* 813 * We subtract 13 from the highest bank bit (13 is the minimum value 814 * allowed by hw) and write the lowest two bits of the remaining value 815 * as hbb_lo and the one above it as hbb_hi to the hardware. 816 */ 817 BUG_ON(cfg->highest_bank_bit < 13); 818 u32 hbb = cfg->highest_bank_bit - 13; 819 bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; 820 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); 821 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); 822 bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; 823 bool min_acc_len_64b = false; 824 u8 uavflagprd_inv = 0; 825 u32 hbb_hi = hbb >> 2; 826 u32 hbb_lo = hbb & 3; 827 828 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 829 uavflagprd_inv = 2; 830 831 if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 832 min_acc_len_64b = true; 833 834 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 835 level2_swizzling_dis << 12 | 836 rgb565_predicator << 11 | 837 hbb_hi << 10 | amsbc << 4 | 838 min_acc_len_64b << 3 | 839 hbb_lo << 1 | ubwc_mode); 840 841 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 842 level2_swizzling_dis << 6 | hbb_hi << 4 | 843 min_acc_len_64b << 3 | 844 hbb_lo << 1 | ubwc_mode); 845 846 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 847 level2_swizzling_dis << 12 | hbb_hi << 10 | 848 uavflagprd_inv << 4 | 849 min_acc_len_64b << 3 | 850 hbb_lo << 1 | ubwc_mode); 851 852 if (adreno_is_a7xx(adreno_gpu)) {
853 for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
854 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 855 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 856 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 857 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 858 } 859 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
860 A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));
861 } 862 863 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 864 min_acc_len_64b << 23 | hbb_lo << 21); 865 866 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 867 cfg->macrotile_mode); 868 } 869
Hi Anna,
kernel test robot noticed the following build errors:
[auto build test ERROR on 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530]
url: https://github.com/intel-lab-lkp/linux/commits/Anna-Maniscalco/drm-msm-Fix-a... base: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 patch link: https://lore.kernel.org/r/20251128-gras_nc_mode_fix-v2-1-634cda7b810f%40gmai... patch subject: [PATCH v2] drm/msm: Fix a7xx per pipe register programming config: loongarch-allmodconfig (https://download.01.org/0day-ci/archive/20251130/202511301632.WkPnj4Dg-lkp@i...) compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251130/202511301632.WkPnj4Dg-lkp@i...)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202511301632.WkPnj4Dg-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:22: error: use of undeclared identifier 'A7XX_PIPE_BR'
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:47: error: use of undeclared identifier 'A7XX_PIPE_BV'
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:860:38: error: use of undeclared identifier 'A7XX_PIPE_NONE'
860 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); | ^ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:22: error: use of undeclared identifier 'A7XX_PIPE_BR' 921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:47: error: use of undeclared identifier 'A7XX_PIPE_BV' 921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { | ^ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:934:38: error: use of undeclared identifier 'A7XX_PIPE_NONE' 934 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); | ^ 6 errors generated.
vim +/A7XX_PIPE_BR +853 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
807 808 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 809 { 810 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 811 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; 812 /* 813 * We subtract 13 from the highest bank bit (13 is the minimum value 814 * allowed by hw) and write the lowest two bits of the remaining value 815 * as hbb_lo and the one above it as hbb_hi to the hardware. 816 */ 817 BUG_ON(cfg->highest_bank_bit < 13); 818 u32 hbb = cfg->highest_bank_bit - 13; 819 bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; 820 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); 821 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); 822 bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; 823 bool min_acc_len_64b = false; 824 u8 uavflagprd_inv = 0; 825 u32 hbb_hi = hbb >> 2; 826 u32 hbb_lo = hbb & 3; 827 828 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 829 uavflagprd_inv = 2; 830 831 if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 832 min_acc_len_64b = true; 833 834 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 835 level2_swizzling_dis << 12 | 836 rgb565_predicator << 11 | 837 hbb_hi << 10 | amsbc << 4 | 838 min_acc_len_64b << 3 | 839 hbb_lo << 1 | ubwc_mode); 840 841 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 842 level2_swizzling_dis << 6 | hbb_hi << 4 | 843 min_acc_len_64b << 3 | 844 hbb_lo << 1 | ubwc_mode); 845 846 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 847 level2_swizzling_dis << 12 | hbb_hi << 10 | 848 uavflagprd_inv << 4 | 849 min_acc_len_64b << 3 | 850 hbb_lo << 1 | ubwc_mode); 851 852 if (adreno_is_a7xx(adreno_gpu)) {
853 for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
854 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 855 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 856 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 857 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 858 } 859 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
860 A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));
861 } 862 863 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 864 min_acc_len_64b << 23 | hbb_lo << 21); 865 866 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 867 cfg->macrotile_mode); 868 } 869
On 11/28/2025 10:47 PM, Anna Maniscalco wrote:
GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe but it needs to be programmed for both.
Program both pipes in hw_init and introducea separate reglist for it in order to add this register to the dynamic reglist which supports restoring registers per pipe.
Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Signed-off-by: Anna Maniscalco anna.maniscalco2000@gmail.com
Changes in v2:
- Added missing Cc: stable to commit
- Added pipe_regs to all 7xx gens
- Null check pipe_regs in a7xx_patch_pwrup_reglist
- Added parentheses around bitwise and in a7xx_patch_pwrup_reglist
- Use A7XX_PIPE_{BR, BV, NONE} enum values
- Link to v1: https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail....
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++++++++++ 4 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 29107b362346..10732062d681 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A6XX_RB_NC_MODE_CNTL, REG_A6XX_RB_CMP_DBG_ECO_CNTL,
- REG_A7XX_GRAS_NC_MODE_CNTL, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, REG_A6XX_UCHE_GBIF_GX_CONFIG, REG_A6XX_UCHE_CLIENT_PF,
@@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = { DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); +static const struct adreno_reglist_pipe a7xx_reglist_pipe_regs[] = {
- { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+};
+DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_reglist_pipe);
static const struct adreno_info a7xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x07000200), @@ -1491,6 +1496,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a730_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020000,@@ -1513,6 +1519,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202,@@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7050001, .gmu_cgc_mode = 0x00020202,@@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202,@@ -1623,6 +1632,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x70f0000, .gmu_cgc_mode = 0x00020222,diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0200a7e71cdf..422ce4c97f70 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode);
- if (adreno_is_a7xx(adreno_gpu))
gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,FIELD_PREP(GENMASK(8, 5), hbb_lo));
- if (adreno_is_a7xx(adreno_gpu)) {
for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,FIELD_PREP(GENMASK(8, 5), hbb_lo));}gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));- }
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len_64b << 23 | hbb_lo << 21); @@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); const struct adreno_reglist_list *reglist;
- const struct adreno_reglist_pipe_list *pipe_reglist; void *ptr = a6xx_gpu->pwrup_reglist_ptr; struct cpu_gpu_lock *lock = ptr; u32 *dest = (u32 *)&lock->regs[0];
- u32 pipe_reglist_count = 0; int i;
lock->gpu_req = lock->cpu_req = lock->turn = 0; @@ -907,7 +916,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) * (<aperture, shifted 12 bits> <address> <data>), and the length is * stored as number for triplets in dynamic_list_len. */
- lock->dynamic_list_len = 0;
- pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist;
- if (pipe_reglist) {
for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
This patch is probably not rebased on msm-next. On msm-next tip, we have removed A7XX prefix for pipe enums.
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));for (i = 0; i < pipe_reglist->count; i++) {if ((pipe_reglist->regs[i].pipe & BIT(pipe_id)) == 0)continue;*dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);*dest++ = pipe_reglist->regs[i].offset;*dest++ = gpu_read(gpu, pipe_reglist->regs[i].offset);pipe_reglist_count++;}}gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));- }
- lock->dynamic_list_len = pipe_reglist_count;
} static int a7xx_preempt_start(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 6820216ec5fc..0a1d6acbc638 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,7 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist;
- const struct adreno_reglist_pipe_list *pipe_reglist;
nit: Maybe dyn_pwrup_reglist is a better name.
Reviewed-by: Akhil P Oommen akhilpo@oss.qualcomm.com
-Akhil
const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; u32 max_slices; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0f8d3de97636..1d0145f8b3ec 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \ .count = ARRAY_SIZE(name ## _regs), \ }; +struct adreno_reglist_pipe_list {
- /** @reg: List of register **/
- const struct adreno_reglist_pipe *regs;
- /** @count: Number of registers in the list **/
- u32 count;
+};
+#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ +static const struct adreno_reglist_pipe_list name = { \
- .regs = name ## _regs, \
- .count = ARRAY_SIZE(name ## _regs), \
+};
struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info;
base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 change-id: 20251126-gras_nc_mode_fix-7224ee506a39
Best regards,
On 12/1/25 5:14 AM, Akhil P Oommen wrote:
On 11/28/2025 10:47 PM, Anna Maniscalco wrote:
GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe but it needs to be programmed for both.
Program both pipes in hw_init and introducea separate reglist for it in order to add this register to the dynamic reglist which supports restoring registers per pipe.
Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Signed-off-by: Anna Maniscalco anna.maniscalco2000@gmail.com
Changes in v2:
- Added missing Cc: stable to commit
- Added pipe_regs to all 7xx gens
- Null check pipe_regs in a7xx_patch_pwrup_reglist
- Added parentheses around bitwise and in a7xx_patch_pwrup_reglist
- Use A7XX_PIPE_{BR, BV, NONE} enum values
- Link to v1: https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail....
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++++++++++ 4 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 29107b362346..10732062d681 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A6XX_RB_NC_MODE_CNTL, REG_A6XX_RB_CMP_DBG_ECO_CNTL,
- REG_A7XX_GRAS_NC_MODE_CNTL, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, REG_A6XX_UCHE_GBIF_GX_CONFIG, REG_A6XX_UCHE_CLIENT_PF,
@@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = { DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); +static const struct adreno_reglist_pipe a7xx_reglist_pipe_regs[] = {
- { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+};
+DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_reglist_pipe);
- static const struct adreno_info a7xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1491,6 +1496,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a730_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020000,@@ -1513,6 +1519,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202,@@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7050001, .gmu_cgc_mode = 0x00020202,@@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist, .ifpc_reglist = &a750_ifpc_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202,@@ -1623,6 +1632,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .pwrup_reglist = &a7xx_pwrup_reglist,
.pipe_reglist = &a7xx_reglist_pipe, .gbif_cx = a640_gbif, .gmu_chipid = 0x70f0000, .gmu_cgc_mode = 0x00020222,diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0200a7e71cdf..422ce4c97f70 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode);
- if (adreno_is_a7xx(adreno_gpu))
gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,FIELD_PREP(GENMASK(8, 5), hbb_lo));
- if (adreno_is_a7xx(adreno_gpu)) {
for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,FIELD_PREP(GENMASK(8, 5), hbb_lo));}gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));- }
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len_64b << 23 | hbb_lo << 21); @@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); const struct adreno_reglist_list *reglist;
- const struct adreno_reglist_pipe_list *pipe_reglist; void *ptr = a6xx_gpu->pwrup_reglist_ptr; struct cpu_gpu_lock *lock = ptr; u32 *dest = (u32 *)&lock->regs[0];
- u32 pipe_reglist_count = 0; int i;
lock->gpu_req = lock->cpu_req = lock->turn = 0; @@ -907,7 +916,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) * (<aperture, shifted 12 bits> <address> <data>), and the length is * stored as number for triplets in dynamic_list_len. */
- lock->dynamic_list_len = 0;
- pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist;
- if (pipe_reglist) {
for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {This patch is probably not rebased on msm-next. On msm-next tip, we have removed A7XX prefix for pipe enums.
Oh no it is rebased that was down to some confusion I made when I was testing with an older branch.
Fixed in v3
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));for (i = 0; i < pipe_reglist->count; i++) {if ((pipe_reglist->regs[i].pipe & BIT(pipe_id)) == 0)continue;*dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);*dest++ = pipe_reglist->regs[i].offset;*dest++ = gpu_read(gpu, pipe_reglist->regs[i].offset);pipe_reglist_count++;}}gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));- }
- lock->dynamic_list_len = pipe_reglist_count; }
static int a7xx_preempt_start(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 6820216ec5fc..0a1d6acbc638 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,7 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist;
- const struct adreno_reglist_pipe_list *pipe_reglist;
nit: Maybe dyn_pwrup_reglist is a better name.
Reviewed-by: Akhil P Oommen akhilpo@oss.qualcomm.com
Agreed, I changed the name in v3. Thx for the review!
-Akhil
const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; u32 max_slices; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0f8d3de97636..1d0145f8b3ec 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \ .count = ARRAY_SIZE(name ## _regs), \ }; +struct adreno_reglist_pipe_list {
- /** @reg: List of register **/
- const struct adreno_reglist_pipe *regs;
- /** @count: Number of registers in the list **/
- u32 count;
+};
+#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ +static const struct adreno_reglist_pipe_list name = { \
- .regs = name ## _regs, \
- .count = ARRAY_SIZE(name ## _regs), \
+};
- struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info;
base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 change-id: 20251126-gras_nc_mode_fix-7224ee506a39
Best regards,
Best regards,
linux-stable-mirror@lists.linaro.org
-
Akhil P Oommen -
Anna Maniscalco -
kernel test robot