This patch series is based on the latest pci/rcar branch of Lorenzo's pci.git. The commit 175cc093888e ("PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()") description/code don't follow the manual accurately, so that it's difficult to understand. So, this patch series reverts the commit at first, and then applies a new fixed patch.
Reference: https://marc.info/?l=linux-renesas-soc&m=157242422327368&w=2
Changes from v1: - Follow -stable rule in patch 1/2. - Add some comments about SPCHG bit of MACCTLR register. https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=195717
Yoshihiro Shimoda (2): Revert "PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" PCI: rcar: Fix missing MACCTLR register setting in initialize sequence
drivers/pci/controller/pcie-rcar.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
This reverts commit 175cc093888ee74a17c4dd5f99ba9a6bc86de5be.
The commit description/code don't follow the manual accurately, it's difficult to understand. So, this patch reverts the commit.
Fixes: 175cc093888e ("PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Cc: stable@vger.kernel.org Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com --- drivers/pci/controller/pcie-rcar.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 0dadccb..40d8c54 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -91,7 +91,6 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 -#define MACCTLR_RESERVED BIT(0) #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -614,8 +613,6 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
- rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); - /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
@@ -1238,7 +1235,6 @@ static int rcar_pcie_resume_noirq(struct device *dev) return 0;
/* Re-establish the PCIe link */ - rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); return rcar_pcie_wait_for_dl(pcie); }
According to the R-Car Gen2/3 manual, "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT". To avoid unexpected behaviors, this patch fixes it. Note that the SPCHG bit of MACCTLR register description said "Only writing 1 is valid and writing 0 is invalid" but this "invalid" means "ignored", not "prohibited". So, any documentation conflict doesn't exist about writing the MACCTLR register.
Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") Cc: stable@vger.kernel.org # v5.2+ Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com --- drivers/pci/controller/pcie-rcar.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 40d8c54..d470ab8 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -91,6 +91,7 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define MACCTLR_INIT_VAL 0x80ff0000 #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
+ rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); + /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
@@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) return 0;
/* Re-establish the PCIe link */ + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); return rcar_pcie_wait_for_dl(pcie); }
Hi Shimoda-san,
On Fri, Nov 01, 2019 at 03:31:30PM +0900, Yoshihiro Shimoda wrote:
According to the R-Car Gen2/3 manual, "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT". To avoid unexpected behaviors, this patch fixes it. Note that the SPCHG bit of MACCTLR register description said "Only writing 1 is valid and writing 0 is invalid" but this "invalid" means "ignored", not "prohibited". So, any documentation conflict doesn't exist about writing the MACCTLR register.
Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") Cc: stable@vger.kernel.org # v5.2+ Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
Reported-by: Eugeniu Rosca erosca@de.adit-jv.com Reviewed-by: Eugeniu Rosca erosca@de.adit-jv.com
Many thanks!
linux-stable-mirror@lists.linaro.org
-
Eugeniu Rosca -
Yoshihiro Shimoda