On Fri, 2024-11-29 at 08:50 +0200, Ville Syrjala wrote:

From: Ville Syrjälä ville.syrjala@linux.intel.com

Mesa changed its clear color alignment from 4k to 64 bytes without informing the kernel side about the change. This is now likely to cause framebuffer creation to fail.

The only thing we do with the clear color buffer in i915 is:

1. map a single page
2. read out bytes 16-23 from said page
3. unmap the page

So the only requirement we really have is that those 8 bytes are all contained within one page. Thus we can deal with the Mesa regression by reducing the alignment requiment from 4k to the same 64 bytes in the kernel. We could even go as low as 32 bytes, but IIRC 64 bytes is the hardware requirement on the 3D engine side so matching that seems sensible.

Cc: stable@vger.kernel.org Cc: Sagar Ghuge sagar.ghuge@intel.com Cc: Nanley Chery nanley.g.chery@intel.com Reported-by: Xi Ruoyao xry111@xry111.site Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13057 Closes: https://lore.kernel.org/all/45a5bba8de009347262d86a4acb27169d9ae0d9f.camel@x... Link: https://gitlab.freedesktop.org/mesa/mesa/-/commit/17f97a69c13832a6c1b0b3aad4... Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com

Tested-by: Xi Ruoyao xry111@xry111.site

---

drivers/gpu/drm/i915/display/intel_fb.c | 2 +-  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 6a7060889f40..223c4218c019 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1694,7 +1694,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *   * arithmetic related to alignment and offset calculation.   */   if (is_gen12_ccs_cc_plane(&fb->base, i)) {

• 	if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
  

• 	if (IS_ALIGNED(fb->base.offsets[i], 64))
  

continue;   else   return -EINVAL;