[PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance IRQ are added to the dts with verification.
[1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hard... [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
Signed-off-by: Yang Xiwen forbidden405@outlook.com --- Changes in v3: - send patches to stable (Andrew Lunn) - rewrite the commit logs more formally (Andrew Lunn) - rename l2-cache0 to l2-cache (Krzysztof Kozlowski) - Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com
Changes in v2: - arm64: dts: hi3798cv200: add GICH, GICV register spces and maintainance IRQ. - Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com
--- Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) --- base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
From: Yang Xiwen forbidden405@outlook.com
During boot, Linux kernel complains:
[ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
This SoC is using a regular GIC-400 and the GICR space size should be 8KB rather than 256B.
With this patch:
[ 0.000000] GIC: Using split EOI/Deactivate mode
So this should be the correct fix.
Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen forbidden405@outlook.com Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller;
From: Yang Xiwen forbidden405@outlook.com
This is needed by KVM to make use of VGIC code. Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified.
Signed-off-by: Yang Xiwen forbidden405@outlook.com --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..fc64d2fa99eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,11 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x2000>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller;
Hi,
Thanks for your patch.
FYI: kernel test robot notices the stable kernel rule is not satisfied.
The check is based on https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html#opti...
Rule: add the tag "Cc: stable@vger.kernel.org" in the sign-off area to have the patch automatically included in the stable tree. Subject: [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Link: https://lore.kernel.org/stable/20240219-cache-v3-2-a33c57534ae9%40outlook.co...
From: Yang Xiwen forbidden405@outlook.com
During boot, the kernel complains:
[ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0
So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)
With this patch, the line above is gone and the following info is added to the output of `lscpu`:
Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance)
Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen forbidden405@outlook.com Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..f6bc001c3832 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; };
cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; };
cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; };
cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; };
+ L2: l2-cache { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance IRQ are added to the dts with verification.
Signed-off-by: Yang Xiwen forbidden405@outlook.com
Changes in v3:
- send patches to stable (Andrew Lunn)
- rewrite the commit logs more formally (Andrew Lunn)
- rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
- Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com
Changes in v2:
- arm64: dts: hi3798cv200: add GICH, GICV register spces and maintainance IRQ.
- Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
Hi Yang,
On 2024/3/12 19:19, Yang Xiwen wrote:
On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance IRQ are added to the dts with verification.
Signed-off-by: Yang Xiwen forbidden405@outlook.com
Changes in v3:
- send patches to stable (Andrew Lunn)
- rewrite the commit logs more formally (Andrew Lunn)
- rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
- Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com
Changes in v2:
- arm64: dts: hi3798cv200: add GICH, GICV register spces and maintainance IRQ.
- Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
Sorry for the delay, I am too busy to catch up with this cycle. I will go through this patch set and maybe apply it during the next cycle.
Best Regards, Wei
On 3/12/2024 7:33 PM, Wei Xu wrote:
Hi Yang,
On 2024/3/12 19:19, Yang Xiwen wrote:
On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance IRQ are added to the dts with verification.
Signed-off-by: Yang Xiwen forbidden405@outlook.com
Changes in v3:
- send patches to stable (Andrew Lunn)
- rewrite the commit logs more formally (Andrew Lunn)
- rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
- Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com
Changes in v2:
- arm64: dts: hi3798cv200: add GICH, GICV register spces and maintainance IRQ.
- Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
Sorry for the delay, I am too busy to catch up with this cycle. I will go through this patch set and maybe apply it during the next cycle.
No problem. I'm just a bit worried if this patch is getting lost. It's good to know it's still maintained. Because i've seen some maintainers not reviewing any patches for over 1 year already, with their names and emails still in MAINTAINERS.
By the way, I think fixes and new features are in different cycles? Most maintainers seem to have multiple branches to handle this.
Best Regards, Wei
Hi Yang,
On 2024/3/12 19:46, Yang Xiwen wrote:
On 3/12/2024 7:33 PM, Wei Xu wrote:
Hi Yang,
On 2024/3/12 19:19, Yang Xiwen wrote:
On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance IRQ are added to the dts with verification.
Signed-off-by: Yang Xiwen forbidden405@outlook.com
Changes in v3:
- send patches to stable (Andrew Lunn)
- rewrite the commit logs more formally (Andrew Lunn)
- rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
- Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com
Changes in v2:
- arm64: dts: hi3798cv200: add GICH, GICV register spces and maintainance IRQ.
- Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
Sorry for the delay, I am too busy to catch up with this cycle. I will go through this patch set and maybe apply it during the next cycle.
No problem. I'm just a bit worried if this patch is getting lost. It's good to know it's still maintained. Because i've seen some maintainers not reviewing any patches for over 1 year already, with their names and emails still in MAINTAINERS.
Thanks for the understanding!
By the way, I think fixes and new features are in different cycles? Most maintainers seem to have multiple branches to handle this.
Yes, they can be in different cycle. But now is the merge window.
Best Regards, Wei
Best Regards, Wei
On 12/03/2024 12:19, Yang Xiwen wrote:
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
It's merge window, what do you expect to happen now? Please observe the process timelines.
For arm-soc usually the cut-off is around rc6. When did you send it? Week before rc6, so a bit late.
Anyway, I bookmarked this patchset, so if no one applies within some time after merge window, I'll take it.
Best regards, Krzysztof
Hi Krzysztof,
On 2024/3/12 19:36, Krzysztof Kozlowski wrote:
On 12/03/2024 12:19, Yang Xiwen wrote:
Yang Xiwen (3): arm64: dts: hi3798cv200: fix the size of GICR arm64: dts: hi3798cv200: add GICH, GICV register space and irq arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2
Best regards,
May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
It's merge window, what do you expect to happen now? Please observe the process timelines.
For arm-soc usually the cut-off is around rc6. When did you send it? Week before rc6, so a bit late.
Anyway, I bookmarked this patchset, so if no one applies within some time after merge window, I'll take it.
Thanks for your explanation and kindness!
Best Regards, Wei
Best regards, Krzysztof
.
On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
[...]
It's rc3 and almost one month after last ping/talk, so apparently these got lost. I'll take them, but let me know if this should go via different tree.
Applied, thanks!
[1/3] arm64: dts: hi3798cv200: fix the size of GICR https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a... [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0a... [3/3] arm64: dts: hi3798cv200: add cache info https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8...
Best regards,
Hi Krzysztof,
On 2024/4/8 15:31, Krzysztof Kozlowski wrote:
On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
[...]
It's rc3 and almost one month after last ping/talk, so apparently these got lost. I'll take them, but let me know if this should go via different tree.
Applied, thanks!
Thanks! Fine to me.
Best Regards, Wei
[1/3] arm64: dts: hi3798cv200: fix the size of GICR https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a... [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0a... [3/3] arm64: dts: hi3798cv200: add cache info https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8...
Best regards,
On 4/8/2024 3:31 PM, Krzysztof Kozlowski wrote:
On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53 Documentation [2].
[...]
It's rc3 and almost one month after last ping/talk, so apparently these got lost. I'll take them, but let me know if this should go via different tree.
Thanks a lot. From my experience, i think this should go via HiSilicon's tree first(which stalls now), then go to SOC tree (git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git), finally in torvald's tree. This was the case for some qcom dts changes about 1yr ago.
Applied, thanks!
[1/3] arm64: dts: hi3798cv200: fix the size of GICR https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a... [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0a... [3/3] arm64: dts: hi3798cv200: add cache info https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8...
Best regards,
linux-stable-mirror@lists.linaro.org
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kernel test robot -
Krzysztof Kozlowski -
Wei Xu -
Yang Xiwen -
Yang Xiwen via B4 Relay