On 11/3/25 23:19, Bjorn Helgaas wrote:

From: Bjorn Helgaas bhelgaas@google.com

Previously meson_pcie_link_up() only returned true if the link was in the L0 state. This was incorrect because hardware autonomously manages transitions between L0, L0s, and L1 while both components on the link stay in D0. Those states should all be treated as "link is active".

Returning false when the device was in L0s or L1 broke config accesses because dw_pcie_other_conf_map_bus() fails if the link is down, which caused errors like this:

meson-pcie fc000000.pcie: error: wait linkup timeout pci 0000:01:00.0: BAR 0: error updating (0xfc700004 != 0xffffffff)

Remove the LTSSM state check, timeout, speed check, and error message from meson_pcie_link_up(), the dw_pcie_ops.link_up() method, so it is a simple boolean check of whether the link is active. Timeouts and and error messages are handled at a higher level, e.g., dw_pcie_wait_for_link().

Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Reported-by: Linnaea Lavia linnaea-von-lavia@live.com Closes: https://lore.kernel.org/r/DM4PR05MB102707B8CDF84D776C39F22F2C7F0A@DM4PR05MB1... Signed-off-by: Bjorn Helgaas bhelgaas@google.com Tested-by: Linnaea Lavia linnaea-von-lavia@live.com Cc: stable@vger.kernel.org

---

drivers/pci/controller/dwc/pci-meson.c | 36 +++----------------------- 1 file changed, 3 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 787469d1b396..13685d89227a 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -338,40 +338,10 @@ static struct pci_ops meson_pci_ops = { static bool meson_pcie_link_up(struct dw_pcie *pci) { struct meson_pcie *mp = to_meson_pcie(pci);

• struct device *dev = pci->dev;
• u32 speed_okay = 0;
• u32 cnt = 0;
• u32 state12, state17, smlh_up, ltssm_up, rdlh_up;

• u32 state12;

• do {

• state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
  

• state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
  

• smlh_up = IS_SMLH_LINK_UP(state12);
  

• rdlh_up = IS_RDLH_LINK_UP(state12);
  

• ltssm_up = IS_LTSSM_UP(state12);
  

• if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
  

• 	speed_okay = 1;
  

• if (smlh_up)
  

• 	dev_dbg(dev, "smlh_link_up is on\n");
  

• if (rdlh_up)
  

• 	dev_dbg(dev, "rdlh_link_up is on\n");
  

• if (ltssm_up)
  

• 	dev_dbg(dev, "ltssm_up is on\n");
  

• if (speed_okay)
  

• 	dev_dbg(dev, "speed_okay\n");
  

• if (smlh_up && rdlh_up && ltssm_up && speed_okay)
  

• 	return true;
  

• cnt++;
  

• udelay(10);
  

• } while (cnt < WAIT_LINKUP_TIMEOUT);
• dev_err(dev, "error: wait linkup timeout\n");
• return false;

• state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
• return IS_SMLH_LINK_UP(state12) && IS_RDLH_LINK_UP(state12); }

static int meson_pcie_host_init(struct dw_pcie_rp *pp)

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Tested-by: Neil Armstrong neil.armstrong@linaro.org # on BananaPi M2S

Thanks !

Neil