On 11/12/2024 5:23 AM, Thinh Nguyen wrote:

On Mon, Nov 11, 2024, Selvarasu Ganesan wrote:

...

The existing implementation of the TxFIFO resizing logic only supports scenarios where more than one port RAM is used. However, there is a need to resize the TxFIFO in USB2.0-only mode where only a single port RAM is available. This commit introduces the necessary changes to support TxFIFO resizing in such scenarios.

Cc: stable@vger.kernel.org # 6.12.x: fad16c82: usb: dwc3: gadget: Refine the logic for resizing Tx FIFOs

You should reword the patch $subject and commit message along the line of adding missing check for single port ram. For this to qualify for stable, emphasize that this is a fix for certain platform configurations. Then add a Fixes tag that can go as far as 9f607a309fbe ("usb: dwc3: Resize TX FIFOs to meet EP bursting requirements")

Thanks for your review comments. And Updated all the your review comments in the below newer version.

https://lore.kernel.org/linux-usb/20241112044807.623-1-selvarasu.g@samsung.c...

Thanks, Selva

...

Signed-off-by: Selvarasu Ganesan selvarasu.g@samsung.com

Changes in v2:  - Removed the code change that limits the number of FIFOs for bulk EP, as plan to address this issue in a separate patch.

• Renamed the variable spram_type to is_single_port_ram for better understanding.
• Link to v1: https://urldefense.com/v3/__https://lore.kernel.org/lkml/20241107104040.502-...

---

drivers/usb/dwc3/core.h | 4 +++ drivers/usb/dwc3/gadget.c | 54 +++++++++++++++++++++++++++++++++------ 2 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index eaa55c0cf62f..8306b39e5c64 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -915,6 +915,7 @@ struct dwc3_hwparams { #define DWC3_MODE(n) ((n) & 0x7) /* HWPARAMS1 */ +#define DWC3_SPRAM_TYPE(n) (((n) >> 23) & 1) #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) /* HWPARAMS3 */ @@ -925,6 +926,9 @@ struct dwc3_hwparams { #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ (DWC3_NUM_IN_EPS_MASK)) >> 18) +/* HWPARAMS6 */ +#define DWC3_RAM0_DEPTH(n) (((n) & (0xffff0000)) >> 16)

• /* HWPARAMS7 */ #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 2fed2aa01407..4f2e063c9091 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -687,6 +687,44 @@ static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult) return fifo_size; } +/**

• • dwc3_gadget_calc_ram_depth - calculates the ram depth for txfifo
• • @dwc: pointer to the DWC3 context
• */

+static int dwc3_gadget_calc_ram_depth(struct dwc3 *dwc) +{

• int ram_depth;
• int fifo_0_start;
• bool is_single_port_ram;
• int tmp;

Try to list this in reversed christmas tree style when possible. Move declaration of tmp under the if (is_single_port_ram) scope.

...

• /* Check supporting RAM type by HW */
• is_single_port_ram = DWC3_SPRAM_TYPE(dwc->hwparams.hwparams1);
• /*

• * If a single port RAM is utilized, then allocate TxFIFOs from
  

• * RAM0. otherwise, allocate them from RAM1.
  

• */
  

• ram_depth = is_single_port_ram ? DWC3_RAM0_DEPTH(dwc->hwparams.hwparams6) :

• 	DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
  

Remove extra new empty line.

...

• /*

• * In a single port RAM configuration, the available RAM is shared
  

• * between the RX and TX FIFOs. This means that the txfifo can begin
  

• * at a non-zero address.
  

• */
  

• if (is_single_port_ram) {

• /* Check if TXFIFOs start at non-zero addr */
  

• tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
  

• fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
  

• ram_depth -= (fifo_0_start >> 16);
  

• }
• return ram_depth;

+}

• /**
  • dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
  • @dwc: pointer to the DWC3 context

@@ -753,7 +791,7 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) { struct dwc3 *dwc = dep->dwc; int fifo_0_start;

• int ram1_depth;

• int ram_depth; int fifo_size; int min_depth; int num_in_ep;

@@ -773,7 +811,7 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) if (dep->flags & DWC3_EP_TXFIFO_RESIZED) return 0;

• ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);

• ram_depth = dwc3_gadget_calc_ram_depth(dwc);

switch (dwc->gadget->speed) { case USB_SPEED_SUPER_PLUS: @@ -809,7 +847,7 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) /* Reserve at least one FIFO for the number of IN EPs */ min_depth = num_in_ep * (fifo + 1);

• remaining = ram1_depth - min_depth - dwc->last_fifo_depth;

• remaining = ram_depth - min_depth - dwc->last_fifo_depth; remaining = max_t(int, 0, remaining); /*
  • We've already reserved 1 FIFO per EP, so check what we can fit in

@@ -835,9 +873,9 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size); /* Check fifo size allocation doesn't exceed available RAM size. */

• if (dwc->last_fifo_depth >= ram1_depth) {

• if (dwc->last_fifo_depth >= ram_depth) { dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",

• 	dwc->last_fifo_depth, ram1_depth,
  

• 	dwc->last_fifo_depth, ram_depth,
  dep->endpoint.name, fifo_size);
  

  if (DWC3_IP_IS(DWC3)) fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);

@@ -3090,7 +3128,7 @@ static int dwc3_gadget_check_config(struct usb_gadget *g) struct dwc3 *dwc = gadget_to_dwc(g); struct usb_ep *ep; int fifo_size = 0;

• int ram1_depth;

• int ram_depth; int ep_num = 0;

if (!dwc->do_fifo_resize) @@ -3113,8 +3151,8 @@ static int dwc3_gadget_check_config(struct usb_gadget *g) fifo_size += dwc->max_cfg_eps; /* Check if we can fit a single fifo per endpoint */

• ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
• if (fifo_size > ram1_depth)

• ram_depth = dwc3_gadget_calc_ram_depth(dwc);
• if (fifo_size > ram_depth) return -ENOMEM;

return 0; -- 2.17.1

Other than minor nits, the rest looks fine.

Thanks, Thinh