This is a note to let you know that I've just added the patch titled

x86/pti: Make sure the user/kernel PTEs match

to the 4.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git%3Ba=su...

The filename of the patch is: x86-pti-make-sure-the-user-kernel-ptes-match.patch and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let stable@vger.kernel.org know about it.

From 52994c256df36fda9a715697431cba9daecb6b11 Mon Sep 17 00:00:00 2001

From: Thomas Gleixner tglx@linutronix.de Date: Wed, 3 Jan 2018 15:57:59 +0100 Subject: x86/pti: Make sure the user/kernel PTEs match

From: Thomas Gleixner tglx@linutronix.de

commit 52994c256df36fda9a715697431cba9daecb6b11 upstream.

Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is enabled:

[Hardware Error]: Error Addr: 0x0000ffff81e000e0 [Hardware Error]: MC1 Error: L1 TLB multimatch. [Hardware Error]: cache level: L1, tx: INSN

The address is in the entry area, which is mapped into kernel _AND_ user space. That's special because we switch CR3 while we are executing there.

User mapping: 0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd

Kernel mapping: 0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd

So the K8 is complaining that the TLB entries differ. They differ in the GLB bit.

Drop the GLB bit when installing the user shared mapping.

Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD") Reported-by: Meelis Roos mroos@linux.ee Signed-off-by: Thomas Gleixner tglx@linutronix.de Tested-by: Meelis Roos mroos@linux.ee Cc: Borislav Petkov bp@alien8.de Cc: Tom Lendacky thomas.lendacky@amd.com Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org

--- arch/x86/mm/pti.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

--- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo static void __init pti_clone_entry_text(void) { pti_clone_pmds((unsigned long) __entry_text_start, - (unsigned long) __irqentry_text_end, _PAGE_RW); + (unsigned long) __irqentry_text_end, + _PAGE_RW | _PAGE_GLOBAL); }

/*

Patches currently in stable-queue which might be from tglx@linutronix.de are

queue-4.14/x86-pti-switch-to-kernel-cr3-at-early-in-entry_syscall_compat.patch queue-4.14/x86-dumpstack-print-registers-for-first-stack-frame.patch queue-4.14/x86-process-define-cpu_tss_rw-in-same-section-as-declaration.patch queue-4.14/x86-pti-make-sure-the-user-kernel-ptes-match.patch queue-4.14/x86-cpu-x86-pti-do-not-enable-pti-on-amd-processors.patch queue-4.14/x86-dumpstack-fix-partial-register-dumps.patch