3 DSC engines are supported only for BMG to be used in specific cases where 12 DSC slices might be required. Add macro for the same and use that while configuring DSC slices.
Ankit Nautiyal (2): drm/i915/display: Add macro for checking 3 DSC engines drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-)
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe.
Bspec: 50175 Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..1a215791d0ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) +#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
Hi,
Thanks for your patch.
FYI: kernel test robot notices the stable kernel rule is not satisfied.
The check is based on https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html#opti...
Rule: add the tag "Cc: stable@vger.kernel.org" in the sign-off area to have the patch automatically included in the stable tree. Subject: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines Link: https://lore.kernel.org/stable/20250414024256.2782702-2-ankit.k.nautiyal%40i...
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 8:13 AM To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: Kandpal, Suraj suraj.kandpal@intel.com; stable@vger.kernel.org; Nautiyal, Ankit K ankit.k.nautiyal@intel.com Subject: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines
3 DSC engines per pipe is currently supported only for BMG.
Would it be better to have a function here which can be modified later to add more platforms in future if they decide to add 3 DSC engine elsewhere too?
Add a macro to check whether a platform supports 3 DSC engines per pipe.
Bspec: 50175 Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..1a215791d0ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)-
has_dp_mst)
#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)-
has_dsc)
+#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(display) == 1401
Shouldn't this be __display instead of just display
Regards, Suraj Kandpal
&& HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)-
fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) -- 2.34.1
On 4/14/2025 9:18 AM, Kandpal, Suraj wrote:
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 8:13 AM To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: Kandpal, Suraj suraj.kandpal@intel.com; stable@vger.kernel.org; Nautiyal, Ankit K ankit.k.nautiyal@intel.com Subject: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines
3 DSC engines per pipe is currently supported only for BMG.
Would it be better to have a function here which can be modified later to add more platforms in future if they decide to add 3 DSC engine elsewhere too?
I was thinking about it too but it seems this is not going to be commonly used and perhaps we can add specific platforms in the macro as well.
Add a macro to check whether a platform supports 3 DSC engines per pipe.
Bspec: 50175 Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..1a215791d0ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)-
has_dp_mst)
#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)-
has_dsc)
+#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(display) == 1401
Shouldn't this be __display instead of just display
You are right, this should have been __display.
Regards,
Ankit
Regards, Suraj Kandpal
&& HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)-
fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) -- 2.34.1
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 9:36 AM To: Kandpal, Suraj suraj.kandpal@intel.com; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: stable@vger.kernel.org Subject: Re: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines
On 4/14/2025 9:18 AM, Kandpal, Suraj wrote:
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 8:13 AM To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: Kandpal, Suraj suraj.kandpal@intel.com; stable@vger.kernel.org; Nautiyal, Ankit K ankit.k.nautiyal@intel.com Subject: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines
3 DSC engines per pipe is currently supported only for BMG.
Would it be better to have a function here which can be modified later to add more platforms in future if they decide to add 3 DSC engine elsewhere
too?
I was thinking about it too but it seems this is not going to be commonly used and perhaps we can add specific platforms in the macro as well.
Ohkay if that’s the case then it seems okay to me
Add a macro to check whether a platform supports 3 DSC engines per pipe.
Bspec: 50175 Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..1a215791d0ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)-
has_dp_mst)
#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)-
has_dsc)
+#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(display) ==
1401
Shouldn't this be __display instead of just display
You are right, this should have been __display.
Regards,
Ankit
Regards, Suraj Kandpal
&& HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)-
fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) -- 2.34.1
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe.
v2:Fix Typo in macro argument. (Suraj). Added fixes tag.
Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..87c666792c0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) +#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 2:27 PM To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: Kandpal, Suraj suraj.kandpal@intel.com; stable@vger.kernel.org; Nautiyal, Ankit K ankit.k.nautiyal@intel.com Subject: [PATCH 1/2] drm/i915/display: Add macro for checking 3 DSC engines
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe.
v2:Fix Typo in macro argument. (Suraj). Added fixes tag.
Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
LGTM, Reviewed-by: Suraj Kandpal suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..87c666792c0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)-
has_dp_mst)
#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)-
has_dsc)
+#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)-
fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) -- 2.34.1
On Mon, 14 Apr 2025, Ankit Nautiyal ankit.k.nautiyal@intel.com wrote:
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe.
Nitpick, feels like a macro returning the number of DSC engines per pipe would be more generic. Like, would you also add HAS_DSC_2ENGINES() and HAS_DSC_4ENGINES() if you needed to know that? But I guess we can go with what you have for the immediate fix.
However, adding the tiniest macro and its only user in separate patches, for something that needs to be backported to stable, seems like erring on the side of splitting up patches too much.
BR, Jani.
v2:Fix Typo in macro argument. (Suraj). Added fixes tag.
Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..87c666792c0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) +#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
On 4/15/2025 12:47 PM, Jani Nikula wrote:
On Mon, 14 Apr 2025, Ankit Nautiyal ankit.k.nautiyal@intel.com wrote:
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe.
Nitpick, feels like a macro returning the number of DSC engines per pipe would be more generic. Like, would you also add HAS_DSC_2ENGINES() and HAS_DSC_4ENGINES() if you needed to know that? But I guess we can go with what you have for the immediate fix.
Yeah NUM_DSC_ENGINES seem better. I was under an impression that newer platforms would have 3 DSC engines, which was incorrect, so specific case for 3 engines made sense at that time.
If there is any further change, I guess returning number of DSC engines as you have suggested is the way to go.
However, adding the tiniest macro and its only user in separate patches, for something that needs to be backported to stable, seems like erring on the side of splitting up patches too much.
Noted. I agree it could have been just one fix with the macro and the usage in same patch.
I have already pushed to drm-intel-next :(. But will keep that in mind.
Thanks Jani for the guidance, thanks Suraj for reviews.
Regards,
Ankit
BR, Jani.
v2:Fix Typo in macro argument. (Suraj). Added fixes tag.
Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..87c666792c0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) +#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
DSC 12 slices configuration is used for some specific cases with Ultrajoiner. This can be supported only when each of the 4 joined pipes have 3 DSC engines each.
Add the missing check for 3 DSC engines support before using 3 DSC slices per pipe.
Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index aeb14a5455fd..d7a30d0992b7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1050,10 +1050,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
/* - * 3 DSC Slices per pipe need 3 DSC engines, - * which is supported only with Ultrajoiner. + * 3 DSC Slices per pipe need 3 DSC engines, which is supported only + * with Ultrajoiner only for some platforms. */ - if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) + if (valid_dsc_slicecount[i] == 3 && + (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) continue;
if (test_slice_count >
-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, April 14, 2025 8:13 AM To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org Cc: Kandpal, Suraj suraj.kandpal@intel.com; stable@vger.kernel.org; Nautiyal, Ankit K ankit.k.nautiyal@intel.com Subject: [PATCH 2/2] drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices
DSC 12 slices configuration is used for some specific cases with Ultrajoiner. This can be supported only when each of the 4 joined pipes have 3 DSC engines each.
Add the missing check for 3 DSC engines support before using 3 DSC slices per pipe.
Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal ankit.k.nautiyal@intel.com Cc: Suraj Kandpal suraj.kandpal@intel.com Cc: stable@vger.kernel.org # v6.14+ Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
LGTM, Reviewed-by: Suraj Kandpal suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index aeb14a5455fd..d7a30d0992b7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1050,10 +1050,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
/*
* 3 DSC Slices per pipe need 3 DSC engines,* which is supported only with Ultrajoiner.
* 3 DSC Slices per pipe need 3 DSC engines, which is supportedonly
* with Ultrajoiner only for some platforms.
if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4)
if (valid_dsc_slicecount[i] == 3 &&(!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) continue;if (test_slice_count >
-- 2.34.1
linux-stable-mirror@lists.linaro.org
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Kandpal, Suraj -
kernel test robot -
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