Hi,
These two patches are backports for 4.4.y stable kernels after one of them failed to apply:
https://lkml.kernel.org/r/156498316752100@kroah.com
Cheers,
Will
--->8
Will Deacon (2): arm64: cpufeature: Fix CTR_EL0 field definitions arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 14 ++++++++++---- 2 files changed, 14 insertions(+), 7 deletions(-)
From: Will Deacon will.deacon@arm.com
commit be68a8aaf925aaf35574260bf820bb09d2f9e07f upstream.
Our field definitions for CTR_EL0 suffer from a number of problems:
- The IDC and DIC fields are missing, which causes us to enable CTR trapping on CPUs with either of these returning non-zero values.
- The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as FTR_HIGHER_SAFE so that applications can use it to avoid false sharing.
- [nit] A RES1 field is described as "RAO"
This patch updates the CTR_EL0 field definitions to fix these issues.
Cc: stable@vger.kernel.org # 4.4.y only Cc: Shanker Donthineni shankerd@codeaurora.org Signed-off-by: Will Deacon will.deacon@arm.com Signed-off-by: Will Deacon will@kernel.org --- arch/arm64/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1eddc07d996..fff0bf2f889e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -126,10 +126,12 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { };
static struct arm64_ftr_bits ftr_ctr[] = { - U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0), + U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0), + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ - U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ /* * Linux can handle differing I-cache policies. Userspace JITs will
commit 147b9635e6347104b91f48ca9dca61eb0fbf2a54 upstream.
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous machines.
Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively saturate at zero.
Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") Cc: stable@vger.kernel.org # 4.4.y only Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com Acked-by: Mark Rutland mark.rutland@arm.com Signed-off-by: Will Deacon will@kernel.org Signed-off-by: Catalin Marinas catalin.marinas@arm.com --- arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 8 ++++++-- 2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ad83c245781c..0a66f8241f18 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -41,9 +41,10 @@
/* CPU feature register tracking */ enum ftr_type { - FTR_EXACT, /* Use a predefined safe value */ - FTR_LOWER_SAFE, /* Smaller value is safe */ - FTR_HIGHER_SAFE,/* Bigger value is safe */ + FTR_EXACT, /* Use a predefined safe value */ + FTR_LOWER_SAFE, /* Smaller value is safe */ + FTR_HIGHER_SAFE, /* Bigger value is safe */ + FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ };
#define FTR_STRICT true /* SANITY check strict matching required */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index fff0bf2f889e..062484d34450 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -130,8 +130,8 @@ static struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0), U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ - U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ - U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */ U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ /* * Linux can handle differing I-cache policies. Userspace JITs will @@ -341,6 +341,10 @@ static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur) case FTR_LOWER_SAFE: ret = new < cur ? new : cur; break; + case FTR_HIGHER_OR_ZERO_SAFE: + if (!cur || !new) + break; + /* Fallthrough */ case FTR_HIGHER_SAFE: ret = new > cur ? new : cur; break;
On Mon, Aug 05, 2019 at 06:13:06PM +0100, Will Deacon wrote:
Hi,
These two patches are backports for 4.4.y stable kernels after one of them failed to apply:
I took these 2, but note that they have two fixes that are not in 4.4:
314d53d297980 arm64: Handle mismatched cache type 4c4a39dd5fe2d arm64: Fix mismatched cache line size detection
Will you send a backport for them?
-- Thanks, Sasha
Hi Sasha, [+Suzuki]
On Tue, Aug 06, 2019 at 05:29:04PM -0400, Sasha Levin wrote:
On Mon, Aug 05, 2019 at 06:13:06PM +0100, Will Deacon wrote:
These two patches are backports for 4.4.y stable kernels after one of them failed to apply:
I took these 2, but note that they have two fixes that are not in 4.4:
314d53d297980 arm64: Handle mismatched cache type 4c4a39dd5fe2d arm64: Fix mismatched cache line size detection
Will you send a backport for them?
4.4 doesn't handle mismatches for the cache type or the line sizes, and instead taints the kernel with a big splat at boot. If we wanted to backport this, we'd need to pick up more than just the above patches, since we don't have the means to emulate user cache maintenance operations either.
Given that the vast majority of systems don't suffer from this problem, I'd be inclined not to try shoe-horning all of this into 4.4, where I think it's more likely introduce other issues.
Suzuki, what do you think?
Will
Hi Will,
On 07/08/2019 10:49, Will Deacon wrote:
Hi Sasha, [+Suzuki]
On Tue, Aug 06, 2019 at 05:29:04PM -0400, Sasha Levin wrote:
On Mon, Aug 05, 2019 at 06:13:06PM +0100, Will Deacon wrote:
These two patches are backports for 4.4.y stable kernels after one of them failed to apply:
I took these 2, but note that they have two fixes that are not in 4.4:
314d53d297980 arm64: Handle mismatched cache type 4c4a39dd5fe2d arm64: Fix mismatched cache line size detection
Will you send a backport for them?
4.4 doesn't handle mismatches for the cache type or the line sizes, and instead taints the kernel with a big splat at boot. If we wanted to backport this, we'd need to pick up more than just the above patches, since we don't have the means to emulate user cache maintenance operations either.
Given that the vast majority of systems don't suffer from this problem, I'd be inclined not to try shoe-horning all of this into 4.4, where I think it's more likely introduce other issues.
Suzuki, what do you think?
I agree. It involves a lot of new code, with non-trivial backports.
Cheers Suzuki
On Wed, Aug 07, 2019 at 11:59:41AM +0100, Suzuki K Poulose wrote:
Hi Will,
On 07/08/2019 10:49, Will Deacon wrote:
Hi Sasha, [+Suzuki]
On Tue, Aug 06, 2019 at 05:29:04PM -0400, Sasha Levin wrote:
On Mon, Aug 05, 2019 at 06:13:06PM +0100, Will Deacon wrote:
These two patches are backports for 4.4.y stable kernels after one of them failed to apply:
I took these 2, but note that they have two fixes that are not in 4.4:
314d53d297980 arm64: Handle mismatched cache type 4c4a39dd5fe2d arm64: Fix mismatched cache line size detection
Will you send a backport for them?
4.4 doesn't handle mismatches for the cache type or the line sizes, and instead taints the kernel with a big splat at boot. If we wanted to backport this, we'd need to pick up more than just the above patches, since we don't have the means to emulate user cache maintenance operations either.
Given that the vast majority of systems don't suffer from this problem, I'd be inclined not to try shoe-horning all of this into 4.4, where I think it's more likely introduce other issues.
Suzuki, what do you think?
I agree. It involves a lot of new code, with non-trivial backports.
Okay, makes sense. Thanks for looking into it.
-- Thanks, Sasha
linux-stable-mirror@lists.linaro.org
-
Sasha Levin -
Suzuki K Poulose -
Will Deacon