From: Pietro Borrello borrello@diag.uniroma1.it

commit 4ab3a086d10eeec1424f2e8a968827a6336203df upstream.

Use spinlocks to deal with workers introducing a wrapper asus_schedule_work(), and several spinlock checks. Otherwise, asus_kbd_backlight_set() may schedule led->work after the structure has been freed, causing a use-after-free.

Fixes: af22a610bc38 ("HID: asus: support backlight on USB keyboards") Signed-off-by: Pietro Borrello borrello@diag.uniroma1.it Link: https://lore.kernel.org/r/20230125-hid-unregister-leds-v4-5-7860c5763c38@dia... Signed-off-by: Benjamin Tissoires benjamin.tissoires@redhat.com Signed-off-by: Stefan Ghinea stefan.ghinea@windriver.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/hid/hid-asus.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)

--- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -491,6 +491,16 @@ static int rog_nkey_led_init(struct hid_ return ret; }

+static void asus_schedule_work(struct asus_kbd_leds *led) +{ + unsigned long flags; + + spin_lock_irqsave(&led->lock, flags); + if (!led->removed) + schedule_work(&led->work); + spin_unlock_irqrestore(&led->lock, flags); +} + static void asus_kbd_backlight_set(struct led_classdev *led_cdev, enum led_brightness brightness) { @@ -502,7 +512,7 @@ static void asus_kbd_backlight_set(struc led->brightness = brightness; spin_unlock_irqrestore(&led->lock, flags);

- schedule_work(&led->work); + asus_schedule_work(led); }

static enum led_brightness asus_kbd_backlight_get(struct led_classdev *led_cdev) @@ -526,9 +536,6 @@ static void asus_kbd_backlight_work(stru int ret; unsigned long flags;

- if (led->removed) - return; - spin_lock_irqsave(&led->lock, flags); buf[4] = led->brightness; spin_unlock_irqrestore(&led->lock, flags);

From: Vasant Hegde vasant.hegde@amd.com

commit f451c7a5a3b818ecfeba2ba258570769998baf3a upstream.

If device->domain is same as new domain then we can skip the device attach process.

Signed-off-by: Vasant Hegde vasant.hegde@amd.com Link: https://lore.kernel.org/r/20230215052642.6016-2-vasant.hegde@amd.com Signed-off-by: Joerg Roedel jroedel@suse.de Cc: "Limonciello, Mario" Mario.Limonciello@amd.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/iommu/amd/iommu.c | 7 +++++++ 1 file changed, 7 insertions(+)

--- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2161,6 +2161,13 @@ static int amd_iommu_attach_device(struc struct amd_iommu *iommu = rlookup_amd_iommu(dev); int ret;

+ /* + * Skip attach device to domain if new domain is same as + * devices current domain + */ + if (dev_data->domain == domain) + return 0; + dev_data->defer_attach = false;

if (dev_data->domain)

From: Vasant Hegde vasant.hegde@amd.com

commit 2cc73c5712f97de98c38c2fafc1f288354a9f3c3 upstream.

iommu_attach_group() attaches all devices in a group to domain and then sets group domain (group->domain). Current code (__iommu_attach_group()) does not handle error path. This creates problem as devices to domain attachment is in inconsistent state.

Flow: - During boot iommu attach devices to default domain - Later some device driver (like amd/iommu_v2 or vfio) tries to attach device to new domain. - In iommu_attach_group() path we detach device from current domain. Then it tries to attach devices to new domain. - If it fails to attach device to new domain then device to domain link is broken. - iommu_attach_group() returns error. - At this stage iommu_attach_group() caller thinks, attaching device to new domain failed and devices are still attached to old domain. - But in reality device to old domain link is broken. It will result in all sort of failures (like IO page fault) later.

To recover from this situation, we need to attach all devices back to the old domain. Also log warning if it fails attach device back to old domain.

Suggested-by: Lu Baolu baolu.lu@linux.intel.com Reported-by: Matt Fagnani matt.fagnani@bell.net Signed-off-by: Vasant Hegde vasant.hegde@amd.com Reviewed-by: Jason Gunthorpe jgg@nvidia.com Tested-by: Matt Fagnani matt.fagnani@bell.net Link: https://lore.kernel.org/r/20230215052642.6016-1-vasant.hegde@amd.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=216865 Link: https://lore.kernel.org/lkml/15d0f9ff-2a56-b3e9-5b45-e6b23300ae3b@leemhuis.i... Signed-off-by: Joerg Roedel jroedel@suse.de Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/iommu/iommu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)

--- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2124,8 +2124,22 @@ static int __iommu_attach_group(struct i

ret = __iommu_group_for_each_dev(group, domain, iommu_group_do_attach_device); - if (ret == 0) + if (ret == 0) { group->domain = domain; + } else { + /* + * To recover from the case when certain device within the + * group fails to attach to the new domain, we need force + * attaching all devices back to the old domain. The old + * domain is compatible for all devices in the group, + * hence the iommu driver should always return success. + */ + struct iommu_domain *old_domain = group->domain; + + group->domain = NULL; + WARN(__iommu_group_set_domain(group, old_domain), + "iommu driver failed to attach a compatible domain"); + }

return ret; }

From: Damien Le Moal damien.lemoal@opensource.wdc.com

commit 6210038aeaf49c395c2da57572246d93ec67f6d4 upstream.

Commit 104ff59af73a ("ata: ahci: Add Tiger Lake UP{3,4} AHCI controller") enabled low power mode for the Tiger Lake AHIC adapter in the author system but created regressions for others. Revert this patch for now until a better solution is found to make this adapter eco-friendly.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=217114 CC: stable@vger.kernel.org Signed-off-by: Damien Le Moal damien.lemoal@opensource.wdc.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/ata/ahci.c | 1 - 1 file changed, 1 deletion(-)

--- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -421,7 +421,6 @@ static const struct pci_device_id ahci_p { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ - { PCI_VDEVICE(INTEL, 0xa0d3), board_ahci_low_power }, /* Tiger Lake UP{3,4} AHCI */

/* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,

From: Dmitry Baryshkov dmitry.baryshkov@linaro.org

[ Upstream commit 41a37d157a613444c97e8f71a5fb2a21116b70d7 ]

The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names for PCIe resets, but it did not change the existing qcs404.dtsi to use these names. Do it now and use symbol names to make it easier to check and modify the dtsi in future.

Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221226042154.2666748-14-dmitry.baryshkov@linaro.... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a9..502dd6db491e2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 {

clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe";

clock-output-names = "pcie_0_pipe_clk"; @@ -1336,12 +1336,12 @@ pcie: pci@10000000 { <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus";

- resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky",

From: Konrad Dybcio konrad.dybcio@linaro.org

[ Upstream commit 01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 ]

In its current form, UFS did not even probe successfully - it failed when trying to set XO (ref_clk) to 300 MHz instead of doing so to the ICE clk. Moreover, the missing reg-names prevented ICE from working or being discovered at all. Fix both of these issues.

As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0.

Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Konrad Dybcio konrad.dybcio@linaro.org Reviewed-by: Iskren Chernev me@iskren.info Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221208201401.530555-1-konrad.dybcio@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf906..3f4017bc667d6 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -704,6 +704,7 @@ opp-202000000 { ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -736,10 +737,10 @@ ufs_mem_hc: ufs@4804000 { <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>;

status = "disabled"; };

From: Marijn Suijten marijn.suijten@somainline.org

[ Upstream commit be8de06dc397c45cb0f3fe04084089c3f06c419f ]

The framebuffer configuration for kumano griffin, written in kumano dtsi (which is overwritten in bahamut dts for its smaller panel) has to use a 1096x2560 configuration as this is what the panel (and framebuffer area) has been initialized to. Downstream userspace also has access to (and uses) this 2.5k mode by default, and only switches the panel to 4k when requested.

Fixes: d0a6ce59ea4e ("arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)") Signed-off-by: Marijn Suijten marijn.suijten@somainline.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221209191733.1458031-1-marijn.suijten@somainline... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index c958a8b167303..fd8c0097072ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -33,9 +33,10 @@ chosen { framebuffer: framebuffer@9c000000 { compatible = "simple-framebuffer"; reg = <0 0x9c000000 0 0x2300000>; - width = <1644>; - height = <3840>; - stride = <(1644 * 4)>; + /* Griffin BL initializes in 2.5k mode, not 4k */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; format = "a8r8g8b8"; /* * That's (going to be) a lot of clocks, but it's necessary due

From: Konrad Dybcio konrad.dybcio@linaro.org

[ Upstream commit 3b2ff50da499178cc418f4b319e279d1b52958ed ]

Fix up the ramoops node to make it match bindings and style:

- remove "removed-dma-pool" - don't pad size to 8 hex digits - change cc-size to ecc-size so that it's used - increase ecc-size from to 16 - remove the zeroed ftrace-size

Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Reported-by: Luca Weiss luca.weiss@fairphone.com Signed-off-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221210102600.589028-1-konrad.dybcio@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c30..00e43a0d2dd67 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -342,13 +342,12 @@ last_log_region: memory@ffbc0000 { };

ramoops: ramoops@ffc00000 { - compatible = "removed-dma-pool", "ramoops"; - reg = <0 0xffc00000 0 0x00100000>; + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - ftrace-size = <0x0>; msg-size = <0x20000 0x20000>; - cc-size = <0x0>; + ecc-size = <16>; no-map; };

From: Dzmitry Sankouski dsankouski@gmail.com

[ Upstream commit 4c881ab73a64cdbf8691e258ef17b740d27040a0 ]

resin node declaration was moved to pm8998.dtsi file (in disabled state). MSM8998 and SDM845 boards defining resin node did not previously have status="okay" and ended up disabled. Re-enable it by using resin node link from pm8998.dtsi with status="okay".

Fixes: f86ae6f23a9e ("arm64: dts: qcom: sagit: add initial device tree for sagit") Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Reviewed-by: Marijn Suijten marijn.suijten@somainline.org Reported-by: Marijn Suijten marijn.suijten@somainline.org Link: https://lore.kernel.org/linux-arm-msm/20221222115922.jlachctn4lxopp7a@SoMain... Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221228115243.201038-1-dsankouski@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 11 +++-------- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 11 +++-------- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 11 +++-------- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 11 +++-------- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 11 +++-------- .../boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 11 +++-------- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 11 +++-------- 7 files changed, 21 insertions(+), 56 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 310f7a2df1e83..510d12c8c5126 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -364,14 +364,9 @@ cam_snapshot_pin_a: cam-snapshot-btn-active-state { }; };

-&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - debounce = <15625>; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 5da87baa2b23b..3bbd5df196bfc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -357,14 +357,9 @@ vib_default: vib-en-state { }; };

-&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEUP>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; };

&qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index f41c6d600ea8c..878801f540c54 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -615,14 +615,9 @@ vol_up_pin_a: vol-up-active-state { }; };

-&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&pmi8998_lpg { diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 1eb423e4be24c..943287804e1a6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -482,14 +482,9 @@ &mss_pil { status = "okay"; };

-&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index bb77ccfdc68c0..e6191602c70a8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -522,14 +522,9 @@ pinconf { }; };

-&pm8998_pon { - volume_down_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&pmi8998_lpg { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index eb6b2b676eca4..1b12b1a4dcbc7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -325,14 +325,9 @@ &pmi8998_wled { qcom,cabc; };

-&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&pmi8998_rradc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 38ba809a95cd6..fba229d0bd108 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -530,14 +530,9 @@ pinconf { }; };

-&pm8998_pon { - resin { - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - compatible = "qcom,pm8941-resin"; - linux,code = <KEY_VOLUMEDOWN>; - debounce = <15625>; - bias-pull-up; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; };

&q6afedai {

From: Konrad Dybcio konrad.dybcio@linaro.org

[ Upstream commit 7c679f2a2af84edbec0c28171af8c42c6da9af14 ]

Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used).

Add these to the PDX213&214 DTSIs to better document the hardware.

Diff between 223 and 224:

pm8350b < gpio-line-names = "NC", /* GPIO_1 */

gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */

< "NC",

	  "CAM_PWR_LD_EN",

pm8350c < "NC",

	  "WLC_TXPWR_EN",

Which is due to different camera power wiring on 213 and lack of an additional SLG51000 PMIC on 214.

Signed-off-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221118152028.59312-3-konrad.dybcio@linaro.org Stable-dep-of: dcc7cd5c46ca ("arm64: dts: qcom: sm8350-sagami: Rectify GPIO keys") Signed-off-by: Sasha Levin sashal@kernel.org --- .../qcom/sm8350-sony-xperia-sagami-pdx214.dts | 23 +++++++++++++++++++ .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 21 +++++++++++++++++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 20 ++++++++++++++++ 3 files changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts index cc650508dc2d6..e6824c8c2774d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -17,3 +17,26 @@ &framebuffer { height = <2520>; stride = <(1080 * 4)>; }; + +&pm8350b_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "NC", + "NC", + "FOCUS_N"; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "NC", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts index d4afaa393c9a9..c6f402c3ef352 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -68,6 +68,15 @@ slg51000_a_ldo7: ldo7 { };

&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "CAM_PWR_LD_EN", + "NC", + "FOCUS_N"; + cam_pwr_a_cs: cam-pwr-a-cs-state { pins = "gpio1"; function = "normal"; @@ -78,6 +87,18 @@ cam_pwr_a_cs: cam-pwr-a-cs-state { }; };

+&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "WLC_TXPWR_EN", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; + &tlmm { gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ "APPS_I2C_0_SCL", diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index a10306d82a3a1..41c4101ec8f08 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -534,6 +534,26 @@ &mpss { firmware-name = "qcom/sm8350/Sony/sagami/modem.mbn"; };

+&pm8350_gpios { + gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */ + "LCD_ID", + "SDR_MMW_THERM", + "RF_ID", + "NC", + "FP_LDO_EN", + "SP_ARI_PWR_ALARM", + "NC", + "G_ASSIST_N", + "PM8350_OPTION"; /* GPIO_10 */ +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "VOL_DOWN_N", + "PMK8350_OPTION"; +}; + &pmk8350_rtc { status = "okay"; };

From: Marijn Suijten marijn.suijten@somainline.org

[ Upstream commit a40f5ae1ea64ab9e981faf47c31817dc4d7923e4 ]

Pinctrl states typically collate multiple related pins. In the case of gpio-keys there's no hardware-defined relation at all except all pins representing a key; and especially on Sony's lena board there's only one pin regardless. Flatten it similar to other boards [1].

As a drive-by fix, clean up the label string.

[1]: https://lore.kernel.org/linux-arm-msm/11174eb6-0a9d-7df1-6f06-da4010f76453@l...

Fixes: 2b8bbe985659 ("arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons") Signed-off-by: Marijn Suijten marijn.suijten@somainline.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221222215906.324092-1-marijn.suijten@somainline.... Signed-off-by: Sasha Levin sashal@kernel.org --- .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 94f77d376662e..4916d0db5b47f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -35,10 +35,10 @@ framebuffer: framebuffer@a0000000 { gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_state>; + pinctrl-0 = <&vol_down_n>;

key-volume-down { - label = "volume_down"; + label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; @@ -305,14 +305,12 @@ touchscreen@48 { };

&pm6350_gpios { - gpio_keys_state: gpio-keys-state { - key-volume-down-pins { - pins = "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <0>; - bias-disable; - input-enable; - }; + vol_down_n: vol-down-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + input-enable; }; };

From: Marijn Suijten marijn.suijten@somainline.org

[ Upstream commit a9f6a13da473bb6c7406d2784d9e3792f6763cba ]

- Remove autorepeat (leave key repetition to userspace); - Remove unneeded status = "okay" (this is the default); - Remove unneeded linux,input-type <EV_KEY> (this is the default for gpio-keys); - Allow the interrupt line for this button to be disabled; - Use a full, descriptive node name; - Set proper bias on the GPIO via pinctrl; - Sort properties; - Replace deprecated gpio-key,wakeup property with wakeup-source.

Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by: Marijn Suijten marijn.suijten@somainline.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221222192443.119103-1-marijn.suijten@somainline.... Signed-off-by: Sasha Levin sashal@kernel.org --- .../qcom/sm6125-sony-xperia-seine-pdx201.dts | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 0de6c5b7f742e..09cff5d1d0ae8 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -41,17 +41,18 @@ extcon_usb: extcon-usb { };

gpio-keys { - status = "okay"; compatible = "gpio-keys"; - autorepeat;

- key-vol-dn { + pinctrl-0 = <&vol_down_n>; + pinctrl-names = "default"; + + key-volume-down { label = "Volume Down"; gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; - gpio-key,wakeup; debounce-interval = <15>; + linux,can-disable; + wakeup-source; }; };

@@ -270,6 +271,14 @@ &sdhc_1 {

&tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + + vol_down_n: vol-down-n-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; };

&usb3 {

From: Qiheng Lin linqiheng@huawei.com

[ Upstream commit 9eedb910a3be0005b88c696a8552c0d4c9937cd4 ]

of_find_compatible_node() returns a node pointer with refcount incremented, we should use of_node_put() on error path. Add missing of_node_put() to avoid refcount leak.

Fixes: 3329659df030 ("ARM: zynq: Simplify SLCR initialization") Signed-off-by: Qiheng Lin linqiheng@huawei.com Link: https://lore.kernel.org/r/20221129140544.41293-1-linqiheng@huawei.com Signed-off-by: Michal Simek michal.simek@amd.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm/mach-zynq/slcr.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 37707614885a5..9765b3f4c2fc5 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -213,6 +213,7 @@ int __init zynq_early_slcr_init(void) zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); + of_node_put(np); return -ENODEV; }

From: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com

[ Upstream commit a9f6721a3c92764582ed12296292fda4a7f2dd25 ]

Assign power domain to the U3PHY1 T-PHY in otder to keep this PHY alive after unused PD shutdown and to be able to completely cut and restore power to it, for example, to save some power during system suspend/sleep.

Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller") Signed-off-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Link: https://lore.kernel.org/r/20221214131117.108008-2-angelogioacchino.delregno@... Signed-off-by: Matthias Brugger matthias.bgg@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c10cfeb1214d5..d6856691fc385 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1549,6 +1549,7 @@ u3phy1: t-phy@11e30000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x11e30000 0xe00>; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; status = "disabled";

u2port1: usb-phy@0 {

From: Chen-Yu Tsai wenst@chromium.org

[ Upstream commit f19f68e56b0c6631984a9f5023035d4bd09612bb ]

The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller.

On the MT8192 this divider is fixed to /2 and is not configurable.

Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input.

Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Chen-Yu Tsai wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Link: https://lore.kernel.org/r/20221201084229.3464449-3-wenst@chromium.org Signed-off-by: Matthias Brugger matthias.bgg@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 424fc89cc6f7c..0d43a32734a37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -29,6 +29,15 @@ aliases { rdma4 = &rdma4; };

+ clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -534,8 +543,7 @@ systimer: timer@10017000 { "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; - clock-names = "clk13m"; + clocks = <&clk13m>; };

pwrap: pwrap@10026000 {

From: Chen-Yu Tsai wenst@chromium.org

[ Upstream commit b391efba57ff085233d5ead5e01817bf4b71d999 ]

The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally. The 13 MHz clock is not a separate oscillator.

Fix this by making the 13 MHz clock a divide-by-2 fixed factor clock, taking its input from the main 26 MHz oscillator.

Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: Chen-Yu Tsai wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Link: https://lore.kernel.org/r/20221201084229.3464449-5-wenst@chromium.org Signed-off-by: Matthias Brugger matthias.bgg@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index c326aeb33a109..857b0c22422f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -214,10 +214,12 @@ l3_0: l3-cache { }; };

- clk13m: oscillator-13m { - compatible = "fixed-clock"; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; #clock-cells = <0>; - clock-frequency = <13000000>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; clock-output-names = "clk13m"; };

From: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org

[ Upstream commit e5011447376e1b050847ccb2ef7933176ce4de41 ]

The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt.

Fixes: dd6459a0890a ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Reported-by: Doug Anderson dianders@chromium.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Reviewed-by: Douglas Anderson dianders@chromium.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221222151319.122398-2-krzysztof.kozlowski@linaro... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 1b12b1a4dcbc7..d2866155dd870 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -467,7 +467,7 @@ sdc2_card_det_n: sd-card-det-n { };

wcd_intr_default: wcd_intr_default { - pins = <54>; + pins = "gpio54"; function = "gpio";

input-enable;

From: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org

[ Upstream commit 1f75745537222172f84783d369bbd1fb2d4b6414 ]

The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size):

spmi@c440000: #address-cells:0:0: 2 was expected

Fixes: 0f9dc5f09fbd ("arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device") Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Reviewed-by: Stephen Boyd swboyd@chromium.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221213101921.47924-1-krzysztof.kozlowski@linaro.... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8a..e45726be81c82 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3274,8 +3274,8 @@ spmi_bus: spmi@c440000 { interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>;

From: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org

[ Upstream commit 76d9e8b4d54ae2cb91a68f0cb82624887de767a7 ]

The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size):

spmi@c440000: #address-cells:0:0: 2 was expected

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Reviewed-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Johan Hovold johan+linaro@kernel.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221213101921.47924-3-krzysztof.kozlowski@linaro.... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 71cf81a8eb4da..d1bc0e60cfd47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2051,8 +2051,8 @@ spmi_bus: spmi@c440000 { interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; };

From: Dmitry Baryshkov dmitry.baryshkov@linaro.org

[ Upstream commit 19e509d5ea229244b9205f8671bb75b13738a1f9 ]

Drop the #clock-cells (probably a leftover from the times before the DP PHY split)

Fixes: eaac4e55a6f4 ("arm64: dts: qcom: sdm845: add displayport node") Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230110042126.702147-1-dmitry.baryshkov@linaro.or... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d6..f36c23e7a2248 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4593,7 +4593,6 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

From: Bjorn Andersson quic_bjorande@quicinc.com

[ Upstream commit fe07640280cd29ac2997a617a1fb5487feef9387 ]

Running GCC_USB30_*_MASTER_CLK at 200MHz requires CX at nominal level, not doing so results in occasional lockups. This was previously hidden by the fact that the display stack incorrectly voted for CX (instead of MMCX).

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Bjorn Andersson quic_bjorande@quicinc.com Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230112135117.3836655-1-quic_bjorande@quicinc.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d1bc0e60cfd47..8363e82369854 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1863,6 +1863,7 @@ usb_0: usb@a6f8800 { "ss_phy_irq";

power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>;

resets = <&gcc GCC_USB30_PRIM_BCR>;

@@ -1917,6 +1918,7 @@ usb_1: usb@a8f8800 { "ss_phy_irq";

power-domains = <&gcc USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>;

resets = <&gcc GCC_USB30_SEC_BCR>;

From: Martin Blumenstingl martin.blumenstingl@googlemail.com

[ Upstream commit cb199de1d3aecb02556d8a6e26393015effa0a9f ]

Node names should use hyphens instead of underscores to not cause warnings.

Fixes: abfaae24ecf3 ("arm64: dts: meson-gxl: add support for JetHub H1") Suggested-by: Vyacheslav Bocharov adeep@lexina.in Signed-off-by: Martin Blumenstingl martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Link: https://lore.kernel.org/r/20230111211350.1461860-3-martin.blumenstingl@googl... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- .../boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 270483e007bc8..bb7412070cb26 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -86,7 +86,7 @@ sdio_pwrseq: sdio-pwrseq { };

&efuse { - bt_mac: bt_mac@6 { + bt_mac: bt-mac@6 { reg = <0x6 0x6>; };

From: Martin Blumenstingl martin.blumenstingl@googlemail.com

[ Upstream commit 8ed5310356bfa47cc6bb4221ae6b21258c52e3d1 ]

Unit names should use hyphens instead of underscores to not cause warnings.

Fixes: bfe59f92d306 ("ARM64: dts: amlogic: gxbb: Enable NVMEM") Suggested-by: Vyacheslav Bocharov adeep@lexina.in Signed-off-by: Martin Blumenstingl martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Link: https://lore.kernel.org/r/20230111211350.1461860-5-martin.blumenstingl@googl... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 5eed15035b674..4371230b8fe31 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -233,7 +233,7 @@ sn: sn@14 { reg = <0x14 0x10>; };

- eth_mac: eth_mac@34 { + eth_mac: eth-mac@34 { reg = <0x34 0x10>; };

From: Martin Blumenstingl martin.blumenstingl@googlemail.com

[ Upstream commit f189c869ad92787ddd753558bcbae89d75825bb6 ]

Node names should be generic and use hyphens instead of underscores to not cause warnings. Also nodes without a reg property should not have a unit-address. Change the scpi_dvfs node to use clock-controller as node name without a unit address (since it does not have a reg property).

Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes") Signed-off-by: Martin Blumenstingl martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Link: https://lore.kernel.org/r/20230111211350.1461860-7-martin.blumenstingl@googl... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 4371230b8fe31..09a016fd828aa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -250,7 +250,7 @@ scpi { scpi_clocks: clocks { compatible = "arm,scpi-clocks";

- scpi_dvfs: scpi_clocks@0 { + scpi_dvfs: clock-controller { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>;

From: Dhruva Gole d-gole@ti.com

[ Upstream commit 6be5d8e5d1804eb4cec29cd8a85dc9cb18683b5d ]

Fixes the clock Device ID's in the DT according to the tisci docs clock identifiers for AM62x

Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Reviewed-by: Bryan Brattlof bb@ti.com Signed-off-by: Dhruva Gole d-gole@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Link: https://lore.kernel.org/r/20230103054840.1133711-1-d-gole@ti.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 072903649d6ee..ae1ec58117c35 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -413,7 +413,7 @@ main_spi0: spi@20100000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 172 0>; + clocks = <&k3_clks 141 0>; status = "disabled"; };

@@ -424,7 +424,7 @@ main_spi1: spi@20110000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 173 0>; + clocks = <&k3_clks 142 0>; status = "disabled"; };

@@ -435,7 +435,7 @@ main_spi2: spi@20120000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 174 0>; + clocks = <&k3_clks 143 0>; status = "disabled"; };

From: Petr Vorel petr.vorel@gmail.com

[ Upstream commit 26a91359aea4d89e7d3646d806eed0f3755b74bd ]

Original google firmware reports 12 MiB: [ 0.000000] cma: Found cont_splash_mem@0, memory base 0x0000000003400000, size 12 MiB, limit 0xffffffffffffffff

which is actually 12*1024*1024 = 0xc00000.

This matches the aosp source [1]: &cont_splash_mem { reg = <0 0x03400000 0 0xc00000>; };

Fixes: 3cb6a271f4b0 ("arm64: dts: qcom: msm8992-bullhead: Fix cont_splash_mem mapping") Fixes: 976d321f32dc ("arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994")

[1] https://android.googlesource.com/kernel/msm.git/+/android-7.0.0_r0.17/arch/a...

Signed-off-by: Petr Vorel petr.vorel@gmail.com Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20221226185440.440968-2-pevik@seznam.cz Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 79de9cc395c4c..123ec67fb385a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) 2015, LGE Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel petr.vorel@gmail.com + * Copyright (c) 2021-2022, Petr Vorel petr.vorel@gmail.com * Copyright (c) 2022, Dominik Kobinski dominikkobinski314@gmail.com */

@@ -49,7 +49,7 @@ ramoops@1ff00000 { };

cont_splash_mem: memory@3400000 { - reg = <0 0x03400000 0 0x1200000>; + reg = <0 0x03400000 0 0xc00000>; no-map; };

From: Dmitry Baryshkov dmitry.baryshkov@linaro.org

[ Upstream commit 0b3aa9aa629c10928e86f6c9666a5e0b14655b2a ]

The slope values used during tsens calibration differ between msm8976 and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC.

Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230101194034.831222-16-dmitry.baryshkov@linaro.o... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index e432512d8716a..668e05185c21e 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -12,6 +12,10 @@ &pmu { interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; };

+&tsens { + compatible = "qcom,msm8956-tsens", "qcom,tsens-v1"; +}; + /* * You might be wondering.. why is it so empty out there? * Well, the SoCs are almost identical.

From: Robert Marko robimarko@gmail.com

[ Upstream commit 100d9c94ccf15b02742c326cd04f422ab729153b ]

Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel.

Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko robimarko@gmail.com Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230113164449.906002-1-robimarko@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 9dcb48ebc4661..90b0abf8bbbcd 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -242,9 +242,9 @@ pcie_qmp1: phy@8e000 { status = "disabled";

pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>;

From: Robert Marko robimarko@gmail.com

[ Upstream commit 2055cb7dccea16bafa3adf9c5e3216949512c34a ]

Current ranges property set in Gen2 PCIe node is incorrect, replace it with the downstream 5.4 QCA kernel value.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko robimarko@gmail.com Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230113164449.906002-3-robimarko@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index f099785facf39..df16ef5a90bb5 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -773,9 +773,9 @@ pcie1: pci@10000000 { phy-names = "pciephy";

ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x10220000 0x10220000 + 0 0xfde0000>; /* non-prefetchable memory */

interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi";

From: Robert Marko robimarko@gmail.com

[ Upstream commit 0e8b90c0256cf9c9589e2cee517dedc987a34355 ]

Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC driver is relying on the old names to match them as they are being used as the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.

This broke parenting as GCC could not find the parent clock, so fix it by changing to the names that driver is expecting.

Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko robimarko@gmail.com Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230113164449.906002-9-robimarko@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e38aa76e54096..4294beeb494fd 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -222,7 +222,7 @@ pcie_phy0: phy@84200 { #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; }; };

@@ -250,7 +250,7 @@ pcie_phy1: phy@8e200 { #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_1_pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; }; };

From: Yang Yingliang yangyingliang@huawei.com

[ Upstream commit 0414a100d6ab32721efa70ab55524540fdfe0ede ]

If platform_device_add() is not called or failed, it should call platform_device_put() in error case.

Fixes: 97933d6ced60 ("ARM: OMAP1: dmtimer: conversion to platform devices") Reported-by: Hulk Robot hulkci@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com Message-Id: 20220701094602.2365099-1-yangyingliang@huawei.com Signed-off-by: Tony Lindgren tony@atomide.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm/mach-omap1/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index f5cd4bbf7566d..81a912c1145a9 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -158,7 +158,7 @@ static int __init omap1_dm_timer_init(void) kfree(pdata);

err_free_pdev: - platform_device_unregister(pdev); + platform_device_put(pdev);

return ret; }

From: Stefan Wahren stefan.wahren@i2se.com

[ Upstream commit afc8dd99840b7fb7190e769a893cda673bc3a907 ]

Booting Linux on a Raspberry Pi based on bcm2835_defconfig there is no display activity.

Enable CONFIG_FB which is nowadays required for CONFIG_FB_SIMPLE and CONFIG_FRAMEBUFFER_CONSOLE.

Fixes: f611b1e7624c ("drm: Avoid circular dependencies for CONFIG_FB") Signed-off-by: Stefan Wahren stefan.wahren@i2se.com Link: https://lore.kernel.org/r/20230113205842.17051-1-stefan.wahren@i2se.com Signed-off-by: Florian Fainelli f.fainelli@gmail.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm/configs/bcm2835_defconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index a51babd178c26..be0c984a66947 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -107,6 +107,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_DRM=y CONFIG_DRM_V3D=y CONFIG_DRM_VC4=y +CONFIG_FB=y CONFIG_FB_SIMPLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y

From: Vaishnav Achath vaishnav.a@ti.com

[ Upstream commit 9ae21ac445e911e3541985c20052fc05d60f6879 ]

The WKUP_PADCONFIG register region in J7200 has multiple non-addressable regions, split the existing wkup_pmx region as follows to avoid the non-addressable regions and include all valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones.

wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)

J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf

Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")

Signed-off-by: Vaishnav Achath vaishnav.a@ti.com Reviewed-by: Jayesh Choudhary j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Link: https://lore.kernel.org/r/20230119042622.22310-1-vaishnav.a@ti.com Signed-off-by: Sasha Levin sashal@kernel.org --- .../dts/ti/k3-j7200-common-proc-board.dts | 2 +- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 29 ++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 6240856e48631..0d39d6b8cc0ca 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -80,7 +80,7 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; };

-&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fe669deba4896..de56a0165bd0c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -56,7 +56,34 @@ chipid@43000014 { wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x34>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@0x4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@0x4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0xec>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@0x4301c174 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>;

From: Angus Chen angus.chen@jaguarmicro.com

[ Upstream commit ebeb49f43c8952f12aa20f03f00d7009edc2d1c5 ]

The function call ida_simple_get maybe fail,we should deal with it. And if ida_simple_get success ,it need to call ida_simple_remove also. BTW,devm_kasprintf can handle id is zero for consistency.

Fixes: e76bdfd7403a ("ARM: imx: Added perf functionality to mmdc driver") Signed-off-by: Angus Chen angus.chen@jaguarmicro.com Signed-off-by: Shawn Guo shawnguo@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm/mach-imx/mmdc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index af12668d0bf51..b9efe9da06e0b 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -99,6 +99,7 @@ struct mmdc_pmu { cpumask_t cpu; struct hrtimer hrtimer; unsigned int active_events; + int id; struct device *dev; struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; struct hlist_node node; @@ -433,8 +434,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, void __iomem *mmdc_base, struct device *dev) { - int mmdc_num; - *pmu_mmdc = (struct mmdc_pmu) { .pmu = (struct pmu) { .task_ctx_nr = perf_invalid_context, @@ -452,15 +451,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, .active_events = 0, };

- mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); + pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);

- return mmdc_num; + return pmu_mmdc->id; }

static int imx_mmdc_remove(struct platform_device *pdev) { struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);

+ ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); perf_pmu_unregister(&pmu_mmdc->pmu); iounmap(pmu_mmdc->mmdc_base); @@ -474,7 +474,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b { struct mmdc_pmu *pmu_mmdc; char *name; - int mmdc_num; int ret; const struct of_device_id *of_id = of_match_device(imx_mmdc_dt_ids, &pdev->dev); @@ -497,14 +496,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b cpuhp_mmdc_state = ret; }

- mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); - pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; - if (mmdc_num == 0) - name = "mmdc"; - else - name = devm_kasprintf(&pdev->dev, - GFP_KERNEL, "mmdc%d", mmdc_num); + ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (ret < 0) + goto pmu_free;

+ name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", ret); + + pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;

hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, @@ -525,6 +524,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b

pmu_register_err: pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); hrtimer_cancel(&pmu_mmdc->hrtimer); pmu_free:

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit 5b7069d72f03c92a0ab919725017394ebce03a81 ]

Fixes: scpi: clocks: 'clock-controller' does not match any of the regexes: '^clocks-[0-9a-f]+$', 'pinctrl-[0-9]+'

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-2-443515289... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 417523dc4cc03..c87df0b2dfdea 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -153,7 +153,7 @@ scpi { scpi_clocks: clocks { compatible = "arm,scpi-clocks";

- scpi_dvfs: clock-controller { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>;

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit a69cb1042cea840bc7b60fea1c26a6b259e68bf2 ]

Fixes: usb@ffe09080: 'phy-supply' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-4-443515289... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi index 22fd43b5fd73c..1916c007cba58 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi @@ -303,7 +303,7 @@ &uart_AO_B {

&usb { status = "okay"; - phy-supply = <&usb_pwr>; + vbus-supply = <&usb_pwr>; };

&spicc1 {

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit 61ff70708b98a85516eccb3755084ac97b42cf48 ]

Fixes: bus@c8834000: rng: {...} should not be valid under {'type': 'object'}

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-6-443515289... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 467d2eaf817b2..11f89bfecb56a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -532,7 +532,7 @@ periphs: bus@c8834000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;

- hwrng: rng { + hwrng: rng@0 { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; };

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit 956f52025c5dd92c80c12e31c99c854086a6fc55 ]

Fixes: pcf8563@51: $nodename:0: 'pcf8563@51' does not match '^rtc(@.*|-[0-9a-f])*$'

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-8-443515289... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi index 1916c007cba58..e1605a9b0a13f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi @@ -217,7 +217,7 @@ &i2c1 { pinctrl-names = "default";

/* RTC */ - pcf8563: pcf8563@51 { + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; status = "okay";

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit 6bb506ed36968207a8832f0143ebc127f0770eef ]

Fixes: adc-keys: 'update-button' does not match any of the regexes: '^button-', 'pinctrl-[0-9]+'

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-10-44351528... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index bcdf55f48a831..4e84ab87cc7db 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -17,7 +17,7 @@ adc-keys { io-channel-names = "buttons"; keyup-threshold-microvolt = <1800000>;

- update-button { + button-update { label = "update"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <1300000>;

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit eee64d8fbbdaab72bbab3e462f3a7b742d20c8c2 ]

Fixes: leds: status: {...} is not of type 'array'

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-12-44351528... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts index 9ef210f17b4aa..393d3cb33b9ee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts @@ -18,7 +18,7 @@ cvbs-connector { leds { compatible = "gpio-leds";

- status { + led { label = "n1:white:status"; gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; default-state = "on";

From: Neil Armstrong neil.armstrong@linaro.org

[ Upstream commit ce9999722656f2433af9029571bc2b99448dda74 ]

Fixes: pmic@1c: '#clock-cells' is a required property pmic@1c: 'switch-supply' does not match any of the regexes: 'pinctrl-[0-9]+'

The switch supply is described by vcc9-supply per bindings documentation.

Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-14-44351528... Signed-off-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index 1e40709610c52..c8e5a0a42b898 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -381,6 +381,7 @@ rk818: pmic@1c { reg = <0x1c>; interrupt-parent = <&gpio_intc>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ + #clock-cells = <1>;

vcc1-supply = <&vdd_sys>; vcc2-supply = <&vdd_sys>; @@ -391,7 +392,6 @@ rk818: pmic@1c { vcc8-supply = <&vcc_2v3>; vcc9-supply = <&vddao_3v3>; boost-supply = <&vdd_sys>; - switch-supply = <&vdd_sys>;

regulators { vddcpu_a: DCDC_REG1 {

From: Waiman Long longman@redhat.com

[ Upstream commit 3f5245538a1964ae186ab7e1636020a41aa63143 ]

Commit:

91d2a812dfb9 ("locking/rwsem: Make handoff writer optimistically spin on owner")

... assumes that when the owner field is changed to NULL, the lock will become free soon. But commit:

48dfb5d2560d ("locking/rwsem: Disable preemption while trying for rwsem lock")

... disabled preemption when acquiring rwsem for write.

However, preemption has not yet been disabled when acquiring a read lock on a rwsem. So a reader can add a RWSEM_READER_BIAS to count without setting owner to signal a reader, got preempted out by a RT task which then spins in the writer slowpath as owner remains NULL leading to live lock.

One easy way to fix this problem is to disable preemption at all the down_read*() and up_read() code paths as implemented in this patch.

Fixes: 91d2a812dfb9 ("locking/rwsem: Make handoff writer optimistically spin on owner") Reported-by: Mukesh Ojha quic_mojha@quicinc.com Suggested-by: Peter Zijlstra peterz@infradead.org Signed-off-by: Waiman Long longman@redhat.com Signed-off-by: Ingo Molnar mingo@kernel.org Link: https://lore.kernel.org/r/20230126003628.365092-3-longman@redhat.com Signed-off-by: Sasha Levin sashal@kernel.org --- kernel/locking/rwsem.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/kernel/locking/rwsem.c b/kernel/locking/rwsem.c index 44873594de031..324fc370b6a68 100644 --- a/kernel/locking/rwsem.c +++ b/kernel/locking/rwsem.c @@ -1092,7 +1092,7 @@ rwsem_down_read_slowpath(struct rw_semaphore *sem, long count, unsigned int stat /* Ordered by sem->wait_lock against rwsem_mark_wake(). */ break; } - schedule(); + schedule_preempt_disabled(); lockevent_inc(rwsem_sleep_reader); }

@@ -1254,14 +1254,20 @@ static struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem) */ static inline int __down_read_common(struct rw_semaphore *sem, int state) { + int ret = 0; long count;

+ preempt_disable(); if (!rwsem_read_trylock(sem, &count)) { - if (IS_ERR(rwsem_down_read_slowpath(sem, count, state))) - return -EINTR; + if (IS_ERR(rwsem_down_read_slowpath(sem, count, state))) { + ret = -EINTR; + goto out; + } DEBUG_RWSEMS_WARN_ON(!is_rwsem_reader_owned(sem), sem); } - return 0; +out: + preempt_enable(); + return ret; }

static inline void __down_read(struct rw_semaphore *sem) @@ -1281,19 +1287,23 @@ static inline int __down_read_killable(struct rw_semaphore *sem)

static inline int __down_read_trylock(struct rw_semaphore *sem) { + int ret = 0; long tmp;

DEBUG_RWSEMS_WARN_ON(sem->magic != sem, sem);

+ preempt_disable(); tmp = atomic_long_read(&sem->count); while (!(tmp & RWSEM_READ_FAILED_MASK)) { if (atomic_long_try_cmpxchg_acquire(&sem->count, &tmp, tmp + RWSEM_READER_BIAS)) { rwsem_set_reader_owned(sem); - return 1; + ret = 1; + break; } } - return 0; + preempt_enable(); + return ret; }

/* @@ -1335,6 +1345,7 @@ static inline void __up_read(struct rw_semaphore *sem) DEBUG_RWSEMS_WARN_ON(sem->magic != sem, sem); DEBUG_RWSEMS_WARN_ON(!is_rwsem_reader_owned(sem), sem);

+ preempt_disable(); rwsem_clear_reader_owned(sem); tmp = atomic_long_add_return_release(-RWSEM_READER_BIAS, &sem->count); DEBUG_RWSEMS_WARN_ON(tmp < 0, sem); @@ -1343,6 +1354,7 @@ static inline void __up_read(struct rw_semaphore *sem) clear_nonspinnable(sem); rwsem_wake(sem); } + preempt_enable(); }

/* @@ -1662,6 +1674,12 @@ void down_read_non_owner(struct rw_semaphore *sem) { might_sleep(); __down_read(sem); + /* + * The owner value for a reader-owned lock is mostly for debugging + * purpose only and is not critical to the correct functioning of + * rwsem. So it is perfectly fine to set it in a preempt-enabled + * context here. + */ __rwsem_set_reader_owned(sem, NULL); } EXPORT_SYMBOL(down_read_non_owner);

From: Thierry Reding treding@nvidia.com

[ Upstream commit 79ed18d9ece474c15a2578e1cc5bfb4fce7a8eb7 ]

Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first.

These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance").

While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools.

Signed-off-by: Thierry Reding treding@nvidia.com Stable-dep-of: 361238cdc525 ("arm64: tegra: Mark host1x as dma-coherent on Tegra194/234") Signed-off-by: Sasha Levin sashal@kernel.org --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 16 +- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 232 +- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 2564 ++++++++--------- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 86 +- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 1730 +++++------ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 470 +-- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 +- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 2322 +++++++-------- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2435 ++++++++-------- .../arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 36 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 519 ++-- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 66 +- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 278 +- .../arm64/boot/dts/nvidia/tegra210-p2595.dtsi | 3 + .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 3 + .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 86 +- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 384 +-- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 66 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 310 +- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 70 +- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 2486 ++++++++-------- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 390 +-- 22 files changed, 7297 insertions(+), 7291 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 3e8dee85d55f2..d4c034ac12447 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1030,6 +1030,14 @@ clk32k_in: clock-32k { gpio-keys { compatible = "gpio-keys";

+ key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -1038,14 +1046,6 @@ switch-lid { debounce-interval = <1>; wakeup-source; }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-source; - }; };

panel: panel { diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 858fc01cecb69..c017764bc27e9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -893,122 +893,6 @@ throttle_heavy: heavy { }; };

- thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <102000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - mem_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - pllx_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - ahub@70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, @@ -1255,6 +1139,122 @@ cpu@1 { }; };

+ thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <102000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + mem_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + pllx_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 47cf2013afcc3..15aa49fc45039 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -13,922 +13,984 @@ / { aconnect@2900000 { status = "okay";

- dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - ahub@2900800 { status = "okay";

- ports { - #address-cells = <1>; - #size-cells = <0>; + i2s@2901000 { + status = "okay";

- port@0 { - reg = <0x0>; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; + port@0 { + reg = <0>; + + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; }; - };

- port@1 { - reg = <0x1>; + i2s1_port: port@1 { + reg = <1>;

- xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@2 { - reg = <0x2>; + i2s@2901100 { + status = "okay";

- xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@3 { - reg = <0x3>; + port@0 { + reg = <0>;

- xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; }; - };

- port@4 { - reg = <0x4>; + i2s2_port: port@1 { + reg = <1>;

- xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@5 { - reg = <0x5>; + i2s@2901200 { + status = "okay";

- xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@6 { - reg = <0x6>; + port@0 { + reg = <0>;

- xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; }; - };

- port@7 { - reg = <0x7>; + i2s3_port: port@1 { + reg = <1>;

- xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@8 { - reg = <0x8>; + i2s@2901300 { + status = "okay";

- xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@9 { - reg = <0x9>; + port@0 { + reg = <0>;

- xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; }; - };

- port@a { - reg = <0xa>; + i2s4_port: port@1 { + reg = <1>;

- xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@b { - reg = <0xb>; + i2s@2901400 { + status = "okay";

- xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@c { - reg = <0xc>; + port@0 { + reg = <0>;

- xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; }; - };

- port@d { - reg = <0xd>; + i2s5_port: port@1 { + reg = <1>;

- xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@e { - reg = <0xe>; + i2s@2901500 { + status = "okay";

- xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@f { - reg = <0xf>; + port@0 { + reg = <0>;

- xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; }; - };

- port@10 { - reg = <0x10>; + i2s6_port: port@1 { + reg = <1>;

- xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; }; }; + };

- port@11 { - reg = <0x11>; + sfc@2902000 { + status = "okay";

- xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + convert-rate = <44100>; + }; }; - };

- port@12 { - reg = <0x12>; + sfc1_out_port: port@1 { + reg = <1>;

- xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + convert-rate = <48000>; + }; }; }; + };

- port@13 { - reg = <0x13>; + sfc@2902200 { + status = "okay";

- xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; }; - };

- xbar_i2s1_port: port@14 { - reg = <0x14>; + sfc2_out_port: port@1 { + reg = <1>;

- xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; }; }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_i2s2_port: port@15 { - reg = <0x15>; + port@0 { + reg = <0>;

- xbar_i2s2_ep: endpoint { - remote-endpoint = <&i2s2_cif_ep>; + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; }; - };

- xbar_i2s3_port: port@16 { - reg = <0x16>; + sfc3_out_port: port@1 { + reg = <1>;

- xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; }; }; + };

- xbar_i2s4_port: port@17 { - reg = <0x17>; + sfc@2902600 { + status = "okay";

- xbar_i2s4_ep: endpoint { - remote-endpoint = <&i2s4_cif_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_i2s5_port: port@18 { - reg = <0x18>; + port@0 { + reg = <0>;

- xbar_i2s5_ep: endpoint { - remote-endpoint = <&i2s5_cif_ep>; + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; }; - };

- xbar_i2s6_port: port@19 { - reg = <0x19>; + sfc4_out_port: port@1 { + reg = <1>;

- xbar_i2s6_ep: endpoint { - remote-endpoint = <&i2s6_cif_ep>; + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; }; }; + };

- xbar_dmic1_port: port@1a { - reg = <0x1a>; + amx@2903000 { + status = "okay";

- xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_dmic2_port: port@1b { - reg = <0x1b>; + port@0 { + reg = <0>;

- xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; }; - };

- xbar_dmic3_port: port@1c { - reg = <0x1c>; + port@1 { + reg = <1>;

- xbar_dmic3_ep: endpoint { - remote-endpoint = <&dmic3_cif_ep>; + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; }; - };

- xbar_dspk1_port: port@1e { - reg = <0x1e>; + port@2 { + reg = <2>;

- xbar_dspk1_ep: endpoint { - remote-endpoint = <&dspk1_cif_ep>; + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; }; - };

- xbar_dspk2_port: port@1f { - reg = <0x1f>; + port@3 { + reg = <3>;

- xbar_dspk2_ep: endpoint { - remote-endpoint = <&dspk2_cif_ep>; + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; }; - };

- xbar_sfc1_in_port: port@20 { - reg = <0x20>; + amx1_out_port: port@4 { + reg = <4>;

- xbar_sfc1_in_ep: endpoint { - remote-endpoint = <&sfc1_cif_in_ep>; + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; }; }; + };

- port@21 { - reg = <0x21>; + amx@2903100 { + status = "okay";

- xbar_sfc1_out_ep: endpoint { - remote-endpoint = <&sfc1_cif_out_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_sfc2_in_port: port@22 { - reg = <0x22>; + port@0 { + reg = <0>;

- xbar_sfc2_in_ep: endpoint { - remote-endpoint = <&sfc2_cif_in_ep>; + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; }; - };

- port@23 { - reg = <0x23>; + port@1 { + reg = <1>;

- xbar_sfc2_out_ep: endpoint { - remote-endpoint = <&sfc2_cif_out_ep>; + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; }; - };

- xbar_sfc3_in_port: port@24 { - reg = <0x24>; + amx2_in3_port: port@2 { + reg = <2>;

- xbar_sfc3_in_ep: endpoint { - remote-endpoint = <&sfc3_cif_in_ep>; + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; }; - };

- port@25 { - reg = <0x25>; + amx2_in4_port: port@3 { + reg = <3>;

- xbar_sfc3_out_ep: endpoint { - remote-endpoint = <&sfc3_cif_out_ep>; + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; }; - };

- xbar_sfc4_in_port: port@26 { - reg = <0x26>; + amx2_out_port: port@4 { + reg = <4>;

- xbar_sfc4_in_ep: endpoint { - remote-endpoint = <&sfc4_cif_in_ep>; + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; }; }; + };

- port@27 { - reg = <0x27>; + amx@2903200 { + status = "okay";

- xbar_sfc4_out_ep: endpoint { - remote-endpoint = <&sfc4_cif_out_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mvc1_in_port: port@28 { - reg = <0x28>; + port@0 { + reg = <0>;

- xbar_mvc1_in_ep: endpoint { - remote-endpoint = <&mvc1_cif_in_ep>; + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; }; - };

- port@29 { - reg = <0x29>; + port@1 { + reg = <1>;

- xbar_mvc1_out_ep: endpoint { - remote-endpoint = <&mvc1_cif_out_ep>; + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; }; - };

- xbar_mvc2_in_port: port@2a { - reg = <0x2a>; + port@2 { + reg = <2>;

- xbar_mvc2_in_ep: endpoint { - remote-endpoint = <&mvc2_cif_in_ep>; + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; }; - };

- port@2b { - reg = <0x2b>; + port@3 { + reg = <3>;

- xbar_mvc2_out_ep: endpoint { - remote-endpoint = <&mvc2_cif_out_ep>; + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; }; - };

- xbar_amx1_in1_port: port@2c { - reg = <0x2c>; + amx3_out_port: port@4 { + reg = <4>;

- xbar_amx1_in1_ep: endpoint { - remote-endpoint = <&amx1_in1_ep>; + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; }; }; + };

- xbar_amx1_in2_port: port@2d { - reg = <0x2d>; + amx@2903300 { + status = "okay";

- xbar_amx1_in2_ep: endpoint { - remote-endpoint = <&amx1_in2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx1_in3_port: port@2e { - reg = <0x2e>; + port@0 { + reg = <0>;

- xbar_amx1_in3_ep: endpoint { - remote-endpoint = <&amx1_in3_ep>; + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; }; - };

- xbar_amx1_in4_port: port@2f { - reg = <0x2f>; + port@1 { + reg = <1>;

- xbar_amx1_in4_ep: endpoint { - remote-endpoint = <&amx1_in4_ep>; + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; }; - };

- port@30 { - reg = <0x30>; + port@2 { + reg = <2>;

- xbar_amx1_out_ep: endpoint { - remote-endpoint = <&amx1_out_ep>; + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; }; - };

- xbar_amx2_in1_port: port@31 { - reg = <0x31>; + port@3 { + reg = <3>;

- xbar_amx2_in1_ep: endpoint { - remote-endpoint = <&amx2_in1_ep>; + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; }; - };

- xbar_amx2_in2_port: port@32 { - reg = <0x32>; + amx4_out_port: port@4 { + reg = <4>;

- xbar_amx2_in2_ep: endpoint { - remote-endpoint = <&amx2_in2_ep>; + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; }; }; + };

- xbar_amx2_in3_port: port@33 { - reg = <0x33>; + adx@2903800 { + status = "okay";

- xbar_amx2_in3_ep: endpoint { - remote-endpoint = <&amx2_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx2_in4_port: port@34 { - reg = <0x34>; + port@0 { + reg = <0>;

- xbar_amx2_in4_ep: endpoint { - remote-endpoint = <&amx2_in4_ep>; + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; }; - };

- port@35 { - reg = <0x35>; + adx1_out1_port: port@1 { + reg = <1>;

- xbar_amx2_out_ep: endpoint { - remote-endpoint = <&amx2_out_ep>; + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; }; - };

- xbar_amx3_in1_port: port@36 { - reg = <0x36>; + adx1_out2_port: port@2 { + reg = <2>;

- xbar_amx3_in1_ep: endpoint { - remote-endpoint = <&amx3_in1_ep>; + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; }; - };

- xbar_amx3_in2_port: port@37 { - reg = <0x37>; + adx1_out3_port: port@3 { + reg = <3>;

- xbar_amx3_in2_ep: endpoint { - remote-endpoint = <&amx3_in2_ep>; + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; }; - };

- xbar_amx3_in3_port: port@38 { - reg = <0x38>; + adx1_out4_port: port@4 { + reg = <4>;

- xbar_amx3_in3_ep: endpoint { - remote-endpoint = <&amx3_in3_ep>; + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; }; }; + };

- xbar_amx3_in4_port: port@39 { - reg = <0x39>; + adx@2903900 { + status = "okay";

- xbar_amx3_in4_ep: endpoint { - remote-endpoint = <&amx3_in4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@3a { - reg = <0x3a>; + port@0 { + reg = <0>;

- xbar_amx3_out_ep: endpoint { - remote-endpoint = <&amx3_out_ep>; + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; }; - };

- xbar_amx4_in1_port: port@3b { - reg = <0x3b>; + adx2_out1_port: port@1 { + reg = <1>;

- xbar_amx4_in1_ep: endpoint { - remote-endpoint = <&amx4_in1_ep>; + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; }; - };

- xbar_amx4_in2_port: port@3c { - reg = <0x3c>; + adx2_out2_port: port@2 { + reg = <2>;

- xbar_amx4_in2_ep: endpoint { - remote-endpoint = <&amx4_in2_ep>; + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; }; - };

- xbar_amx4_in3_port: port@3d { - reg = <0x3d>; + adx2_out3_port: port@3 { + reg = <3>;

- xbar_amx4_in3_ep: endpoint { - remote-endpoint = <&amx4_in3_ep>; + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; }; - };

- xbar_amx4_in4_port: port@3e { - reg = <0x3e>; + adx2_out4_port: port@4 { + reg = <4>;

- xbar_amx4_in4_ep: endpoint { - remote-endpoint = <&amx4_in4_ep>; + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; }; }; + };

- port@3f { - reg = <0x3f>; + adx@2903a00 { + status = "okay";

- xbar_amx4_out_ep: endpoint { - remote-endpoint = <&amx4_out_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_adx1_in_port: port@40 { - reg = <0x40>; + port@0 { + reg = <0>;

- xbar_adx1_in_ep: endpoint { - remote-endpoint = <&adx1_in_ep>; + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; }; - };

- port@41 { - reg = <0x41>; + adx3_out1_port: port@1 { + reg = <1>;

- xbar_adx1_out1_ep: endpoint { - remote-endpoint = <&adx1_out1_ep>; + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; }; - };

- port@42 { - reg = <0x42>; + adx3_out2_port: port@2 { + reg = <2>;

- xbar_adx1_out2_ep: endpoint { - remote-endpoint = <&adx1_out2_ep>; + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; }; - };

- port@43 { - reg = <0x43>; + adx3_out3_port: port@3 { + reg = <3>;

- xbar_adx1_out3_ep: endpoint { - remote-endpoint = <&adx1_out3_ep>; + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; }; - };

- port@44 { - reg = <0x44>; + adx3_out4_port: port@4 { + reg = <4>;

- xbar_adx1_out4_ep: endpoint { - remote-endpoint = <&adx1_out4_ep>; + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; }; }; + };

- xbar_adx2_in_port: port@45 { - reg = <0x45>; + adx@2903b00 { + status = "okay";

- xbar_adx2_in_ep: endpoint { - remote-endpoint = <&adx2_in_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; }; - };

- port@46 { - reg = <0x46>; + adx4_out1_port: port@1 { + reg = <1>;

- xbar_adx2_out1_ep: endpoint { - remote-endpoint = <&adx2_out1_ep>; + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; }; - };

- port@47 { - reg = <0x47>; + adx4_out2_port: port@2 { + reg = <2>;

- xbar_adx2_out2_ep: endpoint { - remote-endpoint = <&adx2_out2_ep>; + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; }; - };

- port@48 { - reg = <0x48>; + adx4_out3_port: port@3 { + reg = <3>;

- xbar_adx2_out3_ep: endpoint { - remote-endpoint = <&adx2_out3_ep>; + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; }; - };

- port@49 { - reg = <0x49>; + adx4_out4_port: port@4 { + reg = <4>;

- xbar_adx2_out4_ep: endpoint { - remote-endpoint = <&adx2_out4_ep>; + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; }; }; + };

- xbar_adx3_in_port: port@4a { - reg = <0x4a>; + dmic@2904000 { + status = "okay";

- xbar_adx3_in_ep: endpoint { - remote-endpoint = <&adx3_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4b { - reg = <0x4b>; + port@0 { + reg = <0>;

- xbar_adx3_out1_ep: endpoint { - remote-endpoint = <&adx3_out1_ep>; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; }; - };

- port@4c { - reg = <0x4c>; + dmic1_port: port@1 { + reg = <1>;

- xbar_adx3_out2_ep: endpoint { - remote-endpoint = <&adx3_out2_ep>; + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@4d { - reg = <0x4d>; + dmic@2904100 { + status = "okay";

- xbar_adx3_out3_ep: endpoint { - remote-endpoint = <&adx3_out3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4e { - reg = <0x4e>; + port@0 { + reg = <0>;

- xbar_adx3_out4_ep: endpoint { - remote-endpoint = <&adx3_out4_ep>; + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; }; - };

- xbar_adx4_in_port: port@4f { - reg = <0x4f>; + dmic2_port: port@1 { + reg = <1>;

- xbar_adx4_in_ep: endpoint { - remote-endpoint = <&adx4_in_ep>; + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@50 { - reg = <0x50>; + dmic@2904200 { + status = "okay";

- xbar_adx4_out1_ep: endpoint { - remote-endpoint = <&adx4_out1_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@51 { - reg = <0x51>; + port@0 { + reg = <0>;

- xbar_adx4_out2_ep: endpoint { - remote-endpoint = <&adx4_out2_ep>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; }; - };

- port@52 { - reg = <0x52>; + dmic3_port: port@1 { + reg = <1>;

- xbar_adx4_out3_ep: endpoint { - remote-endpoint = <&adx4_out3_ep>; + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@53 { - reg = <0x53>; + dspk@2905000 { + status = "okay";

- xbar_adx4_out4_ep: endpoint { - remote-endpoint = <&adx4_out4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in1_port: port@54 { - reg = <0x54>; + port@0 { + reg = <0>;

- xbar_mixer_in1_ep: endpoint { - remote-endpoint = <&mixer_in1_ep>; + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; }; - };

- xbar_mixer_in2_port: port@55 { - reg = <0x55>; + dspk1_port: port@1 { + reg = <1>;

- xbar_mixer_in2_ep: endpoint { - remote-endpoint = <&mixer_in2_ep>; + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- xbar_mixer_in3_port: port@56 { - reg = <0x56>; + dspk@2905100 { + status = "okay";

- xbar_mixer_in3_ep: endpoint { - remote-endpoint = <&mixer_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in4_port: port@57 { - reg = <0x57>; + port@0 { + reg = <0>;

- xbar_mixer_in4_ep: endpoint { - remote-endpoint = <&mixer_in4_ep>; + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; }; - };

- xbar_mixer_in5_port: port@58 { - reg = <0x58>; + dspk2_port: port@1 { + reg = <1>;

- xbar_mixer_in5_ep: endpoint { - remote-endpoint = <&mixer_in5_ep>; + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- xbar_mixer_in6_port: port@59 { - reg = <0x59>; + processing-engine@2908000 { + status = "okay";

- xbar_mixer_in6_ep: endpoint { - remote-endpoint = <&mixer_in6_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in7_port: port@5a { - reg = <0x5a>; + port@0 { + reg = <0x0>;

- xbar_mixer_in7_ep: endpoint { - remote-endpoint = <&mixer_in7_ep>; + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; }; - };

- xbar_mixer_in8_port: port@5b { - reg = <0x5b>; + ope1_out_port: port@1 { + reg = <0x1>;

- xbar_mixer_in8_ep: endpoint { - remote-endpoint = <&mixer_in8_ep>; + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; }; }; + };

- xbar_mixer_in9_port: port@5c { - reg = <0x5c>; + mvc@290a000 { + status = "okay";

- xbar_mixer_in9_ep: endpoint { - remote-endpoint = <&mixer_in9_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in10_port: port@5d { - reg = <0x5d>; + port@0 { + reg = <0>;

- xbar_mixer_in10_ep: endpoint { - remote-endpoint = <&mixer_in10_ep>; + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; }; - };

- port@5e { - reg = <0x5e>; + mvc1_out_port: port@1 { + reg = <1>;

- xbar_mixer_out1_ep: endpoint { - remote-endpoint = <&mixer_out1_ep>; + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; }; }; + };

- port@5f { - reg = <0x5f>; + mvc@290a200 { + status = "okay";

- xbar_mixer_out2_ep: endpoint { - remote-endpoint = <&mixer_out2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@60 { - reg = <0x60>; + port@0 { + reg = <0>;

- xbar_mixer_out3_ep: endpoint { - remote-endpoint = <&mixer_out3_ep>; + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; }; - };

- port@61 { - reg = <0x61>; + mvc2_out_port: port@1 { + reg = <1>;

- xbar_mixer_out4_ep: endpoint { - remote-endpoint = <&mixer_out4_ep>; + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; }; }; + };

- port@62 { - reg = <0x62>; + amixer@290bb00 { + status = "okay";

- xbar_mixer_out5_ep: endpoint { - remote-endpoint = <&mixer_out5_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_asrc_in1_port: port@63 { - reg = <0x63>; + port@0 { + reg = <0x0>;

- xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; }; - };

- port@64 { - reg = <0x64>; + port@1 { + reg = <0x1>;

- xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; }; - };

- xbar_asrc_in2_port: port@65 { - reg = <0x65>; + port@2 { + reg = <0x2>;

- xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; }; - };

- port@66 { - reg = <0x66>; + port@3 { + reg = <0x3>;

- xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; }; - };

- xbar_asrc_in3_port: port@67 { - reg = <0x67>; + port@4 { + reg = <0x4>;

- xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; }; - };

- port@68 { - reg = <0x68>; + port@5 { + reg = <0x5>;

- xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; }; - };

- xbar_asrc_in4_port: port@69 { - reg = <0x69>; + port@6 { + reg = <0x6>;

- xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; }; - };

- port@6a { - reg = <0x6a>; + port@7 { + reg = <0x7>;

- xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; }; - };

- xbar_asrc_in5_port: port@6b { - reg = <0x6b>; + port@8 { + reg = <0x8>;

- xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; }; - };

- port@6c { - reg = <0x6c>; + port@9 { + reg = <0x9>;

- xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; }; - };

- xbar_asrc_in6_port: port@6d { - reg = <0x6d>; + mixer_out1_port: port@a { + reg = <0xa>;

- xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; }; - };

- port@6e { - reg = <0x6e>; + mixer_out2_port: port@b { + reg = <0xb>;

- xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; }; - };

- xbar_asrc_in7_port: port@6f { - reg = <0x6f>; + mixer_out3_port: port@c { + reg = <0xc>;

- xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; }; - };

- xbar_ope1_in_port: port@70 { - reg = <0x70>; + mixer_out4_port: port@d { + reg = <0xd>;

- xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; }; - };

- port@71 { - reg = <0x71>; + mixer_out5_port: port@e { + reg = <0xe>;

- xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; }; }; }; @@ -1102,33 +1164,7 @@ admaif19_ep: endpoint { }; };

- i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; - - i2s@2901100 { + asrc@2910000 { status = "okay";

ports { @@ -1136,1064 +1172,1028 @@ ports { #size-cells = <0>;

port@0 { - reg = <0>; + reg = <0x0>;

- i2s2_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s2_ep>; + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; }; };

- i2s2_port: port@1 { - reg = <1>; + port@1 { + reg = <0x1>;

- i2s2_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; }; }; - }; - }; - - i2s@2901200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>;

- port@0 { - reg = <0>; + port@2 { + reg = <0x2>;

- i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; }; };

- i2s3_port: port@1 { - reg = <1>; + port@3 { + reg = <0x3>;

- i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; }; }; - }; - }; - - i2s@2901300 { - status = "okay";

- ports { - #address-cells = <1>; - #size-cells = <0>; + port@4 { + reg = <0x4>;

- port@0 { - reg = <0>; + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + };

- i2s4_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s4_ep>; + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; }; };

- i2s4_port: port@1 { - reg = <1>; + port@6 { + reg = <0x6>;

- i2s4_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; }; }; - }; - };

- i2s@2901400 { - status = "okay"; + asrc_out1_port: port@7 { + reg = <0x7>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + };

- port@0 { - reg = <0>; + asrc_out2_port: port@8 { + reg = <0x8>;

- i2s5_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s5_ep>; + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; }; };

- i2s5_port: port@1 { - reg = <1>; + asrc_out3_port: port@9 { + reg = <0x9>;

- i2s5_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; }; }; - }; - };

- i2s@2901500 { - status = "okay"; + asrc_out4_port: port@a { + reg = <0xa>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + };

- port@0 { - reg = <0>; + asrc_out5_port: port@b { + reg = <0xb>;

- i2s6_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s6_ep>; + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; }; };

- i2s6_port: port@1 { - reg = <1>; + asrc_out6_port: port@c { + reg = <0xc>;

- i2s6_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; }; }; }; };

- dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@0 { - reg = <0>; + port@0 { + reg = <0x0>;

- dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; }; + };

- dmic1_port: port@1 { - reg = <1>; + port@1 { + reg = <0x1>;

- dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; }; }; - };

- dmic@2904100 { - status = "okay"; + port@2 { + reg = <0x2>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + };

- port@0 { - reg = <0>; + port@3 { + reg = <0x3>;

- dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; }; + };

- dmic2_port: port@1 { - reg = <1>; + port@4 { + reg = <0x4>;

- dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; }; }; - };

- dmic@2904200 { - status = "okay"; + port@5 { + reg = <0x5>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + };

- port@0 { - reg = <0>; + port@6 { + reg = <0x6>;

- dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; }; + };

- dmic3_port: port@1 { - reg = <1>; + port@7 { + reg = <0x7>;

- dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; }; }; - };

- dspk@2905000 { - status = "okay"; + port@8 { + reg = <0x8>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + };

- port@0 { - reg = <0>; + port@9 { + reg = <0x9>;

- dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; }; + };

- dspk1_port: port@1 { - reg = <1>; + port@a { + reg = <0xa>;

- dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; }; }; - };

- dspk@2905100 { - status = "okay"; + port@b { + reg = <0xb>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + };

- port@0 { - reg = <0>; + port@c { + reg = <0xc>;

- dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; }; + };

- dspk2_port: port@1 { - reg = <1>; + port@d { + reg = <0xd>;

- dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; }; }; - };

- sfc@2902000 { - status = "okay"; + port@e { + reg = <0xe>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + };

- port@0 { - reg = <0>; + port@f { + reg = <0xf>;

- sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - convert-rate = <44100>; - }; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; }; + };

- sfc1_out_port: port@1 { - reg = <1>; + port@10 { + reg = <0x10>;

- sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - convert-rate = <48000>; - }; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; }; }; - };

- sfc@2902200 { - status = "okay"; + port@11 { + reg = <0x11>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + };

- port@0 { - reg = <0>; + port@12 { + reg = <0x12>;

- sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; }; + };

- sfc2_out_port: port@1 { - reg = <1>; + port@13 { + reg = <0x13>;

- sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; }; }; - };

- sfc@2902400 { - status = "okay"; + xbar_i2s1_port: port@14 { + reg = <0x14>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_i2s2_port: port@15 { + reg = <0x15>;

- sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; }; + };

- sfc3_out_port: port@1 { - reg = <1>; + xbar_i2s3_port: port@16 { + reg = <0x16>;

- sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; }; }; - };

- sfc@2902600 { - status = "okay"; + xbar_i2s4_port: port@17 { + reg = <0x17>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_i2s5_port: port@18 { + reg = <0x18>;

- sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; }; + };

- sfc4_out_port: port@1 { - reg = <1>; + xbar_i2s6_port: port@19 { + reg = <0x19>;

- sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; }; }; - };

- mvc@290a000 { - status = "okay"; + xbar_dmic1_port: port@1a { + reg = <0x1a>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_dmic2_port: port@1b { + reg = <0x1b>;

- mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; }; + };

- mvc1_out_port: port@1 { - reg = <1>; + xbar_dmic3_port: port@1c { + reg = <0x1c>;

- mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; }; }; - };

- mvc@290a200 { - status = "okay"; + xbar_dspk1_port: port@1e { + reg = <0x1e>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_dspk2_port: port@1f { + reg = <0x1f>;

- mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; }; + };

- mvc2_out_port: port@1 { - reg = <1>; + xbar_sfc1_in_port: port@20 { + reg = <0x20>;

- mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; + xbar_sfc1_in_ep: endpoint { + remote-endpoint = <&sfc1_cif_in_ep>; }; }; - };

- amx@2903000 { - status = "okay"; + port@21 { + reg = <0x21>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_sfc1_out_ep: endpoint { + remote-endpoint = <&sfc1_cif_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_sfc2_in_port: port@22 { + reg = <0x22>;

- amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; + xbar_sfc2_in_ep: endpoint { + remote-endpoint = <&sfc2_cif_in_ep>; }; + };

- port@1 { - reg = <1>; + port@23 { + reg = <0x23>;

- amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; + xbar_sfc2_out_ep: endpoint { + remote-endpoint = <&sfc2_cif_out_ep>; }; + };

- port@2 { - reg = <2>; + xbar_sfc3_in_port: port@24 { + reg = <0x24>;

- amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; + xbar_sfc3_in_ep: endpoint { + remote-endpoint = <&sfc3_cif_in_ep>; }; + };

- port@3 { - reg = <3>; + port@25 { + reg = <0x25>;

- amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; + xbar_sfc3_out_ep: endpoint { + remote-endpoint = <&sfc3_cif_out_ep>; }; + };

- amx1_out_port: port@4 { - reg = <4>; + xbar_sfc4_in_port: port@26 { + reg = <0x26>;

- amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; + xbar_sfc4_in_ep: endpoint { + remote-endpoint = <&sfc4_cif_in_ep>; }; }; - };

- amx@2903100 { - status = "okay"; + port@27 { + reg = <0x27>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_sfc4_out_ep: endpoint { + remote-endpoint = <&sfc4_cif_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_mvc1_in_port: port@28 { + reg = <0x28>;

- amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; + xbar_mvc1_in_ep: endpoint { + remote-endpoint = <&mvc1_cif_in_ep>; }; + };

- port@1 { - reg = <1>; - - amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; + port@29 { + reg = <0x29>; + + xbar_mvc1_out_ep: endpoint { + remote-endpoint = <&mvc1_cif_out_ep>; }; + };

- amx2_in3_port: port@2 { - reg = <2>; + xbar_mvc2_in_port: port@2a { + reg = <0x2a>;

- amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; + xbar_mvc2_in_ep: endpoint { + remote-endpoint = <&mvc2_cif_in_ep>; }; + };

- amx2_in4_port: port@3 { - reg = <3>; + port@2b { + reg = <0x2b>;

- amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; + xbar_mvc2_out_ep: endpoint { + remote-endpoint = <&mvc2_cif_out_ep>; }; + };

- amx2_out_port: port@4 { - reg = <4>; + xbar_amx1_in1_port: port@2c { + reg = <0x2c>;

- amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; + xbar_amx1_in1_ep: endpoint { + remote-endpoint = <&amx1_in1_ep>; }; }; - };

- amx@2903200 { - status = "okay"; + xbar_amx1_in2_port: port@2d { + reg = <0x2d>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx1_in2_ep: endpoint { + remote-endpoint = <&amx1_in2_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx1_in3_port: port@2e { + reg = <0x2e>;

- amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; + xbar_amx1_in3_ep: endpoint { + remote-endpoint = <&amx1_in3_ep>; }; + };

- port@1 { - reg = <1>; + xbar_amx1_in4_port: port@2f { + reg = <0x2f>;

- amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; + xbar_amx1_in4_ep: endpoint { + remote-endpoint = <&amx1_in4_ep>; }; + };

- port@2 { - reg = <2>; + port@30 { + reg = <0x30>;

- amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; + xbar_amx1_out_ep: endpoint { + remote-endpoint = <&amx1_out_ep>; }; + };

- port@3 { - reg = <3>; + xbar_amx2_in1_port: port@31 { + reg = <0x31>;

- amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; + xbar_amx2_in1_ep: endpoint { + remote-endpoint = <&amx2_in1_ep>; }; + };

- amx3_out_port: port@4 { - reg = <4>; + xbar_amx2_in2_port: port@32 { + reg = <0x32>;

- amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; + xbar_amx2_in2_ep: endpoint { + remote-endpoint = <&amx2_in2_ep>; }; }; - };

- amx@2903300 { - status = "okay"; + xbar_amx2_in3_port: port@33 { + reg = <0x33>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx2_in3_ep: endpoint { + remote-endpoint = <&amx2_in3_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx2_in4_port: port@34 { + reg = <0x34>;

- amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; + xbar_amx2_in4_ep: endpoint { + remote-endpoint = <&amx2_in4_ep>; }; + };

- port@1 { - reg = <1>; + port@35 { + reg = <0x35>;

- amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; + xbar_amx2_out_ep: endpoint { + remote-endpoint = <&amx2_out_ep>; }; + };

- port@2 { - reg = <2>; + xbar_amx3_in1_port: port@36 { + reg = <0x36>;

- amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; + xbar_amx3_in1_ep: endpoint { + remote-endpoint = <&amx3_in1_ep>; }; + };

- port@3 { - reg = <3>; + xbar_amx3_in2_port: port@37 { + reg = <0x37>;

- amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; + xbar_amx3_in2_ep: endpoint { + remote-endpoint = <&amx3_in2_ep>; }; + };

- amx4_out_port: port@4 { - reg = <4>; + xbar_amx3_in3_port: port@38 { + reg = <0x38>;

- amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; + xbar_amx3_in3_ep: endpoint { + remote-endpoint = <&amx3_in3_ep>; }; }; - };

- adx@2903800 { - status = "okay"; + xbar_amx3_in4_port: port@39 { + reg = <0x39>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx3_in4_ep: endpoint { + remote-endpoint = <&amx3_in4_ep>; + }; + };

- port@0 { - reg = <0>; + port@3a { + reg = <0x3a>;

- adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; + xbar_amx3_out_ep: endpoint { + remote-endpoint = <&amx3_out_ep>; }; + };

- adx1_out1_port: port@1 { - reg = <1>; + xbar_amx4_in1_port: port@3b { + reg = <0x3b>;

- adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; + xbar_amx4_in1_ep: endpoint { + remote-endpoint = <&amx4_in1_ep>; }; + };

- adx1_out2_port: port@2 { - reg = <2>; + xbar_amx4_in2_port: port@3c { + reg = <0x3c>;

- adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; + xbar_amx4_in2_ep: endpoint { + remote-endpoint = <&amx4_in2_ep>; }; + };

- adx1_out3_port: port@3 { - reg = <3>; + xbar_amx4_in3_port: port@3d { + reg = <0x3d>;

- adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; + xbar_amx4_in3_ep: endpoint { + remote-endpoint = <&amx4_in3_ep>; }; + };

- adx1_out4_port: port@4 { - reg = <4>; + xbar_amx4_in4_port: port@3e { + reg = <0x3e>;

- adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; + xbar_amx4_in4_ep: endpoint { + remote-endpoint = <&amx4_in4_ep>; }; }; - };

- adx@2903900 { - status = "okay"; + port@3f { + reg = <0x3f>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx4_out_ep: endpoint { + remote-endpoint = <&amx4_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_adx1_in_port: port@40 { + reg = <0x40>;

- adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; + xbar_adx1_in_ep: endpoint { + remote-endpoint = <&adx1_in_ep>; }; + };

- adx2_out1_port: port@1 { - reg = <1>; + port@41 { + reg = <0x41>;

- adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; + xbar_adx1_out1_ep: endpoint { + remote-endpoint = <&adx1_out1_ep>; }; + };

- adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; + port@42 { + reg = <0x42>; + + xbar_adx1_out2_ep: endpoint { + remote-endpoint = <&adx1_out2_ep>; }; + };

- adx2_out3_port: port@3 { - reg = <3>; + port@43 { + reg = <0x43>;

- adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; + xbar_adx1_out3_ep: endpoint { + remote-endpoint = <&adx1_out3_ep>; }; + };

- adx2_out4_port: port@4 { - reg = <4>; + port@44 { + reg = <0x44>;

- adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; + xbar_adx1_out4_ep: endpoint { + remote-endpoint = <&adx1_out4_ep>; }; }; - };

- adx@2903a00 { - status = "okay"; + xbar_adx2_in_port: port@45 { + reg = <0x45>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx2_in_ep: endpoint { + remote-endpoint = <&adx2_in_ep>; + }; + };

- port@0 { - reg = <0>; + port@46 { + reg = <0x46>;

- adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; + xbar_adx2_out1_ep: endpoint { + remote-endpoint = <&adx2_out1_ep>; }; + };

- adx3_out1_port: port@1 { - reg = <1>; + port@47 { + reg = <0x47>;

- adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; + xbar_adx2_out2_ep: endpoint { + remote-endpoint = <&adx2_out2_ep>; }; + };

- adx3_out2_port: port@2 { - reg = <2>; + port@48 { + reg = <0x48>;

- adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; + xbar_adx2_out3_ep: endpoint { + remote-endpoint = <&adx2_out3_ep>; }; + };

- adx3_out3_port: port@3 { - reg = <3>; + port@49 { + reg = <0x49>;

- adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; + xbar_adx2_out4_ep: endpoint { + remote-endpoint = <&adx2_out4_ep>; }; + };

- adx3_out4_port: port@4 { - reg = <4>; + xbar_adx3_in_port: port@4a { + reg = <0x4a>;

- adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; + xbar_adx3_in_ep: endpoint { + remote-endpoint = <&adx3_in_ep>; }; }; - };

- adx@2903b00 { - status = "okay"; + port@4b { + reg = <0x4b>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx3_out1_ep: endpoint { + remote-endpoint = <&adx3_out1_ep>; + }; + };

- port@0 { - reg = <0>; + port@4c { + reg = <0x4c>;

- adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; + xbar_adx3_out2_ep: endpoint { + remote-endpoint = <&adx3_out2_ep>; }; + };

- adx4_out1_port: port@1 { - reg = <1>; + port@4d { + reg = <0x4d>;

- adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; + xbar_adx3_out3_ep: endpoint { + remote-endpoint = <&adx3_out3_ep>; }; + };

- adx4_out2_port: port@2 { - reg = <2>; + port@4e { + reg = <0x4e>;

- adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; + xbar_adx3_out4_ep: endpoint { + remote-endpoint = <&adx3_out4_ep>; }; + };

- adx4_out3_port: port@3 { - reg = <3>; + xbar_adx4_in_port: port@4f { + reg = <0x4f>;

- adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; + xbar_adx4_in_ep: endpoint { + remote-endpoint = <&adx4_in_ep>; }; + };

- adx4_out4_port: port@4 { - reg = <4>; + port@50 { + reg = <0x50>;

- adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; + xbar_adx4_out1_ep: endpoint { + remote-endpoint = <&adx4_out1_ep>; }; }; - };

- processing-engine@2908000 { - status = "okay"; + port@51 { + reg = <0x51>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx4_out2_ep: endpoint { + remote-endpoint = <&adx4_out2_ep>; + }; + };

- port@0 { - reg = <0x0>; + port@52 { + reg = <0x52>;

- ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; + xbar_adx4_out3_ep: endpoint { + remote-endpoint = <&adx4_out3_ep>; }; + };

- ope1_out_port: port@1 { - reg = <0x1>; + port@53 { + reg = <0x53>;

- ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; + xbar_adx4_out4_ep: endpoint { + remote-endpoint = <&adx4_out4_ep>; }; }; - };

- amixer@290bb00 { - status = "okay"; + xbar_mixer_in1_port: port@54 { + reg = <0x54>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_mixer_in1_ep: endpoint { + remote-endpoint = <&mixer_in1_ep>; + }; + };

- port@0 { - reg = <0x0>; + xbar_mixer_in2_port: port@55 { + reg = <0x55>;

- mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; + xbar_mixer_in2_ep: endpoint { + remote-endpoint = <&mixer_in2_ep>; }; + };

- port@1 { - reg = <0x1>; + xbar_mixer_in3_port: port@56 { + reg = <0x56>;

- mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; + xbar_mixer_in3_ep: endpoint { + remote-endpoint = <&mixer_in3_ep>; }; + };

- port@2 { - reg = <0x2>; + xbar_mixer_in4_port: port@57 { + reg = <0x57>;

- mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; + xbar_mixer_in4_ep: endpoint { + remote-endpoint = <&mixer_in4_ep>; }; + };

- port@3 { - reg = <0x3>; + xbar_mixer_in5_port: port@58 { + reg = <0x58>;

- mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; + xbar_mixer_in5_ep: endpoint { + remote-endpoint = <&mixer_in5_ep>; }; + };

- port@4 { - reg = <0x4>; + xbar_mixer_in6_port: port@59 { + reg = <0x59>;

- mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; + xbar_mixer_in6_ep: endpoint { + remote-endpoint = <&mixer_in6_ep>; }; + };

- port@5 { - reg = <0x5>; + xbar_mixer_in7_port: port@5a { + reg = <0x5a>;

- mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; + xbar_mixer_in7_ep: endpoint { + remote-endpoint = <&mixer_in7_ep>; }; + };

- port@6 { - reg = <0x6>; - - mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; + xbar_mixer_in8_port: port@5b { + reg = <0x5b>; + + xbar_mixer_in8_ep: endpoint { + remote-endpoint = <&mixer_in8_ep>; }; + };

- port@7 { - reg = <0x7>; + xbar_mixer_in9_port: port@5c { + reg = <0x5c>;

- mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; + xbar_mixer_in9_ep: endpoint { + remote-endpoint = <&mixer_in9_ep>; }; + };

- port@8 { - reg = <0x8>; + xbar_mixer_in10_port: port@5d { + reg = <0x5d>;

- mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; + xbar_mixer_in10_ep: endpoint { + remote-endpoint = <&mixer_in10_ep>; }; + };

- port@9 { - reg = <0x9>; + port@5e { + reg = <0x5e>;

- mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; + xbar_mixer_out1_ep: endpoint { + remote-endpoint = <&mixer_out1_ep>; }; + };

- mixer_out1_port: port@a { - reg = <0xa>; + port@5f { + reg = <0x5f>;

- mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; + xbar_mixer_out2_ep: endpoint { + remote-endpoint = <&mixer_out2_ep>; }; + };

- mixer_out2_port: port@b { - reg = <0xb>; + port@60 { + reg = <0x60>;

- mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; + xbar_mixer_out3_ep: endpoint { + remote-endpoint = <&mixer_out3_ep>; }; + };

- mixer_out3_port: port@c { - reg = <0xc>; + port@61 { + reg = <0x61>;

- mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; + xbar_mixer_out4_ep: endpoint { + remote-endpoint = <&mixer_out4_ep>; }; + };

- mixer_out4_port: port@d { - reg = <0xd>; + port@62 { + reg = <0x62>;

- mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; + xbar_mixer_out5_ep: endpoint { + remote-endpoint = <&mixer_out5_ep>; }; + };

- mixer_out5_port: port@e { - reg = <0xe>; + xbar_asrc_in1_port: port@63 { + reg = <0x63>;

- mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; }; }; - };

- asrc@2910000 { - status = "okay"; + port@64 { + reg = <0x64>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + };

- port@0 { - reg = <0x0>; + xbar_asrc_in2_port: port@65 { + reg = <0x65>;

- asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; }; + };

- port@1 { - reg = <0x1>; + port@66 { + reg = <0x66>;

- asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; }; + };

- port@2 { - reg = <0x2>; + xbar_asrc_in3_port: port@67 { + reg = <0x67>;

- asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; }; + };

- port@3 { - reg = <0x3>; + port@68 { + reg = <0x68>;

- asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; }; + };

- port@4 { - reg = <0x4>; + xbar_asrc_in4_port: port@69 { + reg = <0x69>;

- asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; }; + };

- port@5 { - reg = <0x5>; + port@6a { + reg = <0x6a>;

- asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; }; + };

- port@6 { - reg = <0x6>; + xbar_asrc_in5_port: port@6b { + reg = <0x6b>;

- asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; }; + };

- asrc_out1_port: port@7 { - reg = <0x7>; + port@6c { + reg = <0x6c>;

- asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; }; + };

- asrc_out2_port: port@8 { - reg = <0x8>; + xbar_asrc_in6_port: port@6d { + reg = <0x6d>;

- asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; }; + };

- asrc_out3_port: port@9 { - reg = <0x9>; + port@6e { + reg = <0x6e>;

- asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; }; + };

- asrc_out4_port: port@a { - reg = <0xa>; + xbar_asrc_in7_port: port@6f { + reg = <0x6f>;

- asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; }; + };

- asrc_out5_port: port@b { - reg = <0xb>; + xbar_ope1_in_port: port@70 { + reg = <0x70>;

- asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; }; + };

- asrc_out6_port: port@c { - reg = <0xc>; + port@71 { + reg = <0x71>;

- asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; }; }; }; }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; };

i2c@3160000 { @@ -2283,6 +2283,10 @@ mmc@3400000 { vmmc-supply = <&vdd_sd>; };

+ sata@3507000 { + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson TX2 HDA"; status = "okay"; @@ -2471,10 +2475,6 @@ dpaux@155c0000 { }; };

- sata@3507000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys";

@@ -2489,21 +2489,21 @@ key-power { wakeup-source; };

- key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; + linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; };

- key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; + linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index aff857df25cf4..a4264ea417285 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -190,32 +190,6 @@ pmc@c360000 { nvidia,invert-interrupt; };

- cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - bpmp { i2c { status = "okay"; @@ -235,6 +209,23 @@ pmic: pmic@3c { pinctrl-names = "default"; pinctrl-0 = <&max77620_default>;

+ fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -284,23 +275,6 @@ gpio7 { }; };

- fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; @@ -387,6 +361,32 @@ vdd_pex: ldo8 { }; };

+ cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 3e83a4d52eb1e..26f71651933d1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -56,679 +56,282 @@ phy: ethernet-phy@0 { }; };

- memory-controller@2c00000 { - status = "okay"; - }; - - timer@3010000 { + aconnect@2900000 { status = "okay"; - };

- serial@3100000 { - status = "okay"; - }; + ahub@2900800 { + status = "okay";

- i2c@3160000 { - status = "okay"; - }; + i2s@2901000 { + status = "okay";

- i2c@3180000 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>;

- power-monitor@40 { - compatible = "ti,ina3221"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; + port@0 { + reg = <0>;

- input@0 { - reg = <0>; - label = "VDD_IN"; - shunt-resistor-micro-ohms = <5>; - }; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + };

- input@1 { - reg = <1>; - label = "VDD_CPU_GPU"; - shunt-resistor-micro-ohms = <5>; - }; + i2s1_port: port@1 { + reg = <1>;

- input@2 { - reg = <2>; - label = "VDD_SOC"; - shunt-resistor-micro-ohms = <5>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; }; - }; - };

- ddc: i2c@3190000 { - status = "okay"; - }; + i2s@2901200 { + status = "okay";

- i2c@31c0000 { - status = "okay"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- i2c@31e0000 { - status = "okay"; - }; + port@0 { + reg = <0>;

- /* SDMMC4 (eMMC) */ - mmc@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + };

- vqmmc-supply = <&vdd_1v8_ap>; - vmmc-supply = <&vdd_3v3_sys>; - }; + i2s3_port: port@1 { + reg = <1>;

- hda@3510000 { - nvidia,model = "NVIDIA Jetson TX2 NX HDA"; - status = "okay"; - }; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + };

- padctl@3520000 { - status = "okay"; + dmic@2904000 { + status = "okay";

- avdd-pll-erefeut-supply = <&vdd_1v8_pll>; - avdd-usb-supply = <&vdd_3v3_sys>; - vclamp-usb-supply = <&vdd_1v8>; - vddio-hsic-supply = <&gnd>; + ports { + #address-cells = <1>; + #size-cells = <0>;

- pads { - usb2 { - status = "okay"; + port@0 { + reg = <0>;

- lanes { - micro_b: usb2-0 { - nvidia,function = "xusb"; - status = "okay"; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; };

- usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; + dmic1_port: port@1 { + reg = <1>;

- usb2-2 { - nvidia,function = "xusb"; - status = "okay"; + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; };

- usb3 { + dmic@2904100 { status = "okay";

- lanes { - usb3-1 { - nvidia,function = "xusb"; - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; }; - }; - }; - };

- ports { - usb2-0 { - status = "okay"; - mode = "otg"; - vbus-supply = <&vdd_5v0_sys>; - usb-role-switch; + dmic2_port: port@1 { + reg = <1>;

- connector { - compatible = "gpio-usb-b-connector", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - vbus-gpios = <&gpio - TEGRA186_MAIN_GPIO(L, 4) - GPIO_ACTIVE_LOW>; - id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; }; };

- usb2-1 { + admaif@290f000 { status = "okay"; - mode = "host";

- vbus-supply = <&vdd_5v0_sys>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- usb2-2 { - status = "okay"; - mode = "host"; + admaif0_port: port@0 { + reg = <0x0>;

- vbus-supply = <&vdd_5v0_sys>; - }; + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + };

- usb3-1 { - nvidia,usb2-companion = <1>; - vbus-supply = <&vdd_5v0_sys>; - status = "okay"; - }; - }; - }; + admaif1_port: port@1 { + reg = <0x1>;

- usb@3530000 { - status = "okay"; + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + };

- phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@3520000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@3520000/pads/usb3/lanes/usb3-1}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-1"; - }; + admaif2_port: port@2 { + reg = <0x2>;

- usb@3550000 { - status = "okay"; + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + };

- phys = <&micro_b>; - phy-names = "usb2-0"; - }; + admaif3_port: port@3 { + reg = <0x3>;

- hsp@3c00000 { - status = "okay"; - }; + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + };

- i2c@c240000 { - status = "okay"; - }; + admaif4_port: port@4 { + reg = <0x4>;

- i2c@c250000 { - status = "okay"; + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + };

- /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; + admaif5_port: port@5 { + reg = <0x5>;

- label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - - /* carrier board ID EEPROM */ - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pwm@c340000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - - pcie@10003000 { - status = "okay"; - - dvdd-pex-supply = <&vdd_pex>; - hvdd-pex-pll-supply = <&vdd_1v8>; - hvdd-pex-supply = <&vdd_1v8>; - vddio-pexctl-aud-supply = <&vdd_1v8>; - - pci@1,0 { - nvidia,num-lanes = <2>; - status = "okay"; - }; - - pci@2,0 { - nvidia,num-lanes = <1>; - status = "disabled"; - }; - - pci@3,0 { - nvidia,num-lanes = <1>; - status = "okay"; - }; - }; - - host1x@13e00000 { - status = "okay"; - - dpaux@15040000 { - status = "okay"; - }; - - display-hub@15200000 { - status = "okay"; - }; - - dsi@15300000 { - status = "disabled"; - }; - - /* DP */ - sor@15540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; - - nvidia,dpaux = <&dpaux>; - }; - - /* HDMI */ - sor@15580000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) - GPIO_ACTIVE_LOW>; - }; - - dpaux@155c0000 { - status = "okay"; - }; - }; - - gpu@17000000 { - status = "okay"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - - interrupt-parent = <&pmc>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = <MAX77620_FPS_SRC_0>; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = <MAX77620_FPS_SRC_1>; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = <MAX77620_FPS_SRC_1>; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio5 { - pins = "gpio5"; - function = "gpio"; - drive-push-pull = <0>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; };

- gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; + admaif6_port: port@6 { + reg = <0x6>;

- fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; };

- fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; + admaif7_port: port@7 { + reg = <0x7>;

- fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>;

- in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_1v8>; - in-ldo7-8-supply = <&avdd_dsi_csi>; + admaif8_port: port@8 { + reg = <0x8>;

- sd0 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; };

- avdd_dsi_csi: sd1 { - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; + admaif9_port: port@9 { + reg = <0x9>;

- vdd_1v8: sd2 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; };

- vdd_3v3_sys: sd3 { - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + admaif10_port: port@a { + reg = <0xa>;

- vdd_1v8_pll: ldo0 { - regulator-name = "VDD_1V8_AP_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; };

- ldo2 { - regulator-name = "VDDIO_3V3_AOHV"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; + admaif11_port: port@b { + reg = <0xb>;

- vddio_sdmmc1: ldo3 { - regulator-name = "VDDIO_SDMMC1_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; };

- ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; + admaif12_port: port@c { + reg = <0xc>;

- vddio_sdmmc3: ldo5 { - regulator-name = "VDDIO_SDMMC3_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; };

- vdd_hdmi_1v05: ldo7 { - regulator-name = "VDD_HDMI_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; + admaif13_port: port@d { + reg = <0xd>;

- vdd_pex: ldo8 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; }; - }; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - gnd: regulator-gnd { - compatible = "regulator-fixed"; - regulator-name = "GND"; - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator-vdd-5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_ap: regulator-vdd-1v8-ap { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_1v8>; - }; - - vdd_hdmi: regulator-vdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vdd_5v0_sys>; - }; - - thermal-zones { - cpu-thermal { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <79000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <62000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <45000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - };

- cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; + admaif14_port: port@e { + reg = <0xe>;

- cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + };

- cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; + admaif15_port: port@f { + reg = <0xf>;

- aux-thermal { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + };

- trips { - aux_alert0: critical { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; + admaif16_port: port@10 { + reg = <0x10>;

- gpu-thermal { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + };

- trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; + admaif17_port: port@11 { + reg = <0x11>;

- aconnect@2900000 { - status = "okay"; + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + };

- dma-controller@2930000 { - status = "okay"; - }; + admaif18_port: port@12 { + reg = <0x12>;

- interrupt-controller@2a40000 { - status = "okay"; - }; + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + };

- ahub@2900800 { - status = "okay"; + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + };

ports { #address-cells = <1>; @@ -809,395 +412,708 @@ xbar_admaif8_ep: endpoint { port@9 { reg = <0x9>;

- xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + + memory-controller@2c00000 { + status = "okay"; + }; + + timer@3010000 { + status = "okay"; + }; + + serial@3100000 { + status = "okay"; + }; + + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + + power-monitor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0>; + label = "VDD_IN"; + shunt-resistor-micro-ohms = <5>; + }; + + input@1 { + reg = <1>; + label = "VDD_CPU_GPU"; + shunt-resistor-micro-ohms = <5>; + }; + + input@2 { + reg = <2>; + label = "VDD_SOC"; + shunt-resistor-micro-ohms = <5>; + }; + }; + }; + + ddc: i2c@3190000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + }; + + i2c@31e0000 { + status = "okay"; + };

- port@a { - reg = <0xa>; + /* SDMMC4 (eMMC) */ + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable;

- xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; + vqmmc-supply = <&vdd_1v8_ap>; + vmmc-supply = <&vdd_3v3_sys>; + };

- port@b { - reg = <0xb>; + hda@3510000 { + nvidia,model = "NVIDIA Jetson TX2 NX HDA"; + status = "okay"; + };

- xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; + padctl@3520000 { + status = "okay";

- port@c { - reg = <0xc>; + avdd-pll-erefeut-supply = <&vdd_1v8_pll>; + avdd-usb-supply = <&vdd_3v3_sys>; + vclamp-usb-supply = <&vdd_1v8>; + vddio-hsic-supply = <&gnd>;

- xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; + pads { + usb2 { + status = "okay"; + + lanes { + micro_b: usb2-0 { + nvidia,function = "xusb"; + status = "okay"; }; - };

- port@d { - reg = <0xd>; + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + };

- xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; }; }; + };

- port@e { - reg = <0xe>; + usb3 { + status = "okay";

- xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; + lanes { + usb3-1 { + nvidia,function = "xusb"; + status = "okay"; }; }; + }; + };

- port@f { - reg = <0xf>; + ports { + usb2-0 { + status = "okay"; + mode = "otg"; + vbus-supply = <&vdd_5v0_sys>; + usb-role-switch;

- xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpios = <&gpio + TEGRA186_MAIN_GPIO(L, 4) + GPIO_ACTIVE_LOW>; + id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; }; + };

- port@10 { - reg = <0x10>; + usb2-1 { + status = "okay"; + mode = "host";

- xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; + vbus-supply = <&vdd_5v0_sys>; + };

- port@11 { - reg = <0x11>; + usb2-2 { + status = "okay"; + mode = "host";

- xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; - }; - }; + vbus-supply = <&vdd_5v0_sys>; + };

- port@12 { - reg = <0x12>; + usb3-1 { + nvidia,usb2-companion = <1>; + vbus-supply = <&vdd_5v0_sys>; + status = "okay"; + }; + }; + };

- xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; + usb@3530000 { + status = "okay";

- port@13 { - reg = <0x13>; + phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-1"; + };

- xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; + usb@3550000 { + status = "okay";

- xbar_i2s1_port: port@14 { - reg = <0x14>; + phys = <&micro_b>; + phy-names = "usb2-0"; + };

- xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; - }; - }; + hsp@3c00000 { + status = "okay"; + };

- xbar_i2s3_port: port@16 { - reg = <0x16>; + i2c@c240000 { + status = "okay"; + };

- xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; - }; - }; + i2c@c250000 { + status = "okay";

- xbar_dmic1_port: port@1a { - reg = <0x1a>; + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>;

- xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; + label = "module"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + };

- xbar_dmic2_port: port@1b { - reg = <0x1b>; + /* carrier board ID EEPROM */ + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>;

- xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; - }; - }; - }; + label = "system"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + };

- admaif@290f000 { - status = "okay"; + rtc@c2a0000 { + status = "okay"; + };

- ports { - #address-cells = <1>; - #size-cells = <0>; + pwm@c340000 { + status = "okay"; + };

- admaif0_port: port@0 { - reg = <0x0>; + pmc@c360000 { + nvidia,invert-interrupt; + };

- admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; + pcie@10003000 { + status = "okay";

- admaif1_port: port@1 { - reg = <0x1>; + dvdd-pex-supply = <&vdd_pex>; + hvdd-pex-pll-supply = <&vdd_1v8>; + hvdd-pex-supply = <&vdd_1v8>; + vddio-pexctl-aud-supply = <&vdd_1v8>;

- admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; + pci@1,0 { + nvidia,num-lanes = <2>; + status = "okay"; + };

- admaif2_port: port@2 { - reg = <0x2>; + pci@2,0 { + nvidia,num-lanes = <1>; + status = "disabled"; + };

- admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; + pci@3,0 { + nvidia,num-lanes = <1>; + status = "okay"; + }; + };

- admaif3_port: port@3 { - reg = <0x3>; + host1x@13e00000 { + status = "okay";

- admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; + dpaux@15040000 { + status = "okay"; + };

- admaif4_port: port@4 { - reg = <0x4>; + display-hub@15200000 { + status = "okay"; + };

- admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; + dsi@15300000 { + status = "disabled"; + };

- admaif5_port: port@5 { - reg = <0x5>; + /* DP */ + sor@15540000 { + status = "okay";

- admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; + avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;

- admaif6_port: port@6 { - reg = <0x6>; + nvidia,dpaux = <&dpaux>; + };

- admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; + /* HDMI */ + sor@15580000 { + status = "okay";

- admaif7_port: port@7 { - reg = <0x7>; + avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; + hdmi-supply = <&vdd_hdmi>;

- admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; + nvidia,ddc-i2c-bus = <&ddc>; + nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) + GPIO_ACTIVE_LOW>; + };

- admaif8_port: port@8 { - reg = <0x8>; + dpaux@155c0000 { + status = "okay"; + }; + };

- admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; + gpu@17000000 { + status = "okay"; + };

- admaif9_port: port@9 { - reg = <0x9>; + bpmp { + i2c { + status = "okay";

- admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; + pmic: pmic@3c { + compatible = "maxim,max77620"; + reg = <0x3c>;

- admaif10_port: port@a { - reg = <0xa>; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <2>; + interrupt-controller;

- admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; + #gpio-cells = <2>; + gpio-controller;

- admaif11_port: port@b { - reg = <0xb>; + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>;

- admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; };

- admaif12_port: port@c { - reg = <0xc>; + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + };

- admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; }; + };

- admaif13_port: port@d { - reg = <0xd>; + max77620_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + };

- admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; + gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; };

- admaif14_port: port@e { - reg = <0xe>; + gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + };

- admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; + gpio3 { + pins = "gpio3"; + function = "fps-out"; + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; };

- admaif15_port: port@f { - reg = <0xf>; + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + drive-push-pull = <1>; + };

- admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; + gpio5 { + pins = "gpio5"; + function = "gpio"; + drive-push-pull = <0>; };

- admaif16_port: port@10 { - reg = <0x10>; + gpio6 { + pins = "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + };

- admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; + gpio7 { + pins = "gpio7"; + function = "gpio"; + drive-push-pull = <1>; }; + };

- admaif17_port: port@11 { - reg = <0x11>; + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>;

- admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; + in-ldo0-1-supply = <&vdd_5v0_sys>; + in-ldo2-supply = <&vdd_5v0_sys>; + in-ldo3-5-supply = <&vdd_5v0_sys>; + in-ldo4-6-supply = <&vdd_1v8>; + in-ldo7-8-supply = <&avdd_dsi_csi>; + + sd0 { + regulator-name = "VDD_DDR_1V1_PMIC"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; };

- admaif18_port: port@12 { - reg = <0x12>; + avdd_dsi_csi: sd1 { + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + };

- admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; + vdd_1v8: sd2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; };

- admaif19_port: port@13 { - reg = <0x13>; + vdd_3v3_sys: sd3 { + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + };

- admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; + vdd_1v8_pll: ldo0 { + regulator-name = "VDD_1V8_AP_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - }; - };

- i2s@2901000 { - status = "okay"; + ldo2 { + regulator-name = "VDDIO_3V3_AOHV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + };

- ports { - #address-cells = <1>; - #size-cells = <0>; + vddio_sdmmc1: ldo3 { + regulator-name = "VDDIO_SDMMC1_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + };

- port@0 { - reg = <0>; + ldo4 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + };

- i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; + vddio_sdmmc3: ldo5 { + regulator-name = "VDDIO_SDMMC3_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; };

- i2s1_port: port@1 { - reg = <1>; + vdd_hdmi_1v05: ldo7 { + regulator-name = "VDD_HDMI_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + };

- i2s1_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; + vdd_pex: ldo8 { + regulator-name = "VDD_PEX_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; }; }; }; + }; + };

- i2s@2901200 { - status = "okay"; + cpus { + cpu@0 { + enable-method = "psci"; + };

- ports { - #address-cells = <1>; - #size-cells = <0>; + cpu@1 { + enable-method = "psci"; + };

- port@0 { - reg = <0>; + cpu@2 { + enable-method = "psci"; + };

- i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; - }; - }; + cpu@3 { + enable-method = "psci"; + };

- i2s3_port: port@1 { - reg = <1>; + cpu@4 { + enable-method = "psci"; + };

- i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; + cpu@5 { + enable-method = "psci"; + }; + };

- dmic@2904000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys";

- ports { - #address-cells = <1>; - #size-cells = <0>; + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + };

- port@0 { - reg = <0>; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + };

- dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + }; + };

- dmic1_port: port@1 { - reg = <1>; + psci { + compatible = "arm,psci-1.0"; + status = "okay"; + method = "smc"; + };

- dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>;

- dmic@2904100 { - status = "okay"; + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + };

- ports { - #address-cells = <1>; - #size-cells = <0>; + gnd: regulator-gnd { + compatible = "regulator-fixed"; + regulator-name = "GND"; + regulator-min-microvolt = <0>; + regulator-max-microvolt = <0>; + regulator-always-on; + regulator-boot-on; + };

- port@0 { - reg = <0>; + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + };

- dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; + vdd_1v8_ap: regulator-vdd-1v8-ap { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>;

- dmic2_port: port@1 { - reg = <1>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high;

- dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - }; + vin-supply = <&vdd_1v8>; + }; + + vdd_hdmi: regulator-vdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vdd_5v0_sys>; };

sound { @@ -1219,4 +1135,88 @@ sound {

label = "NVIDIA Jetson TX2 NX APE"; }; + + thermal-zones { + cpu-thermal { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + cpu_trip_critical: critical { + temperature = <96500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <79000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active: active { + temperature = <62000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-critical { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_critical>; + }; + + cpu-hot { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_hot>; + }; + + cpu-active { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + + aux-thermal { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + aux_alert0: critical { + temperature = <90000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + gpu_alert0: critical { + temperature = <99000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b3f1494c02c11..0216b565a3703 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -129,62 +129,6 @@ aconnect@2900000 { ranges = <0x02900000 0x0 0x02900000 0x200000>; status = "disabled";

- adma: dma-controller@2930000 { - compatible = "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra186-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = <GIC_SPI 145 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&bpmp TEGRA186_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra186-ahub"; reg = <0x02900800 0x800>; @@ -197,52 +141,6 @@ tegra_ahub: ahub@2900800 { ranges = <0x02900800 0x02900800 0x11800>; status = "disabled";

- tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - }; - tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; @@ -327,78 +225,6 @@ tegra_i2s6: i2s@2901500 { status = "disabled"; };

- tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; @@ -431,22 +257,6 @@ tegra_sfc4: sfc@2902600 { status = "disabled"; };

- tegra_mvc1: mvc@290a000 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@290a200 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@2903000 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; @@ -511,6 +321,78 @@ tegra_adx4: adx@2903b00 { status = "disabled"; };

+ tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra186-ope", "nvidia,tegra210-ope"; @@ -534,6 +416,22 @@ dynamic-range-compressor@2908200 { }; };

+ tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; @@ -542,6 +440,52 @@ tegra_amixer: amixer@290bb00 { status = "disabled"; };

+ tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra186-asrc"; reg = <0x2910000 0x2000>; @@ -549,6 +493,62 @@ tegra_asrc: asrc@2910000 { status = "disabled"; }; }; + + adma: dma-controller@2930000 { + compatible = "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra186-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA186_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; };

mc: memory-controller@2c00000 { @@ -970,6 +970,34 @@ sdmmc4: mmc@3460000 { status = "disabled"; };

+ sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + hda@3510000 { compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; reg = <0x0 0x03510000 0x0 0x10000>; @@ -1286,18 +1314,13 @@ pmc: pmc@c360000 { #interrupt-cells = <2>; interrupt-controller;

- sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; };

- sdmmc2_3v3: sdmmc2-3v3 { - pins = "sdmmc2-hv"; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; };

@@ -1306,8 +1329,8 @@ sdmmc2_1v8: sdmmc2-1v8 { power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; };

- sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + sdmmc2_3v3: sdmmc2-3v3 { + pins = "sdmmc2-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; };

@@ -1315,6 +1338,11 @@ sdmmc3_1v8: sdmmc3-1v8 { pins = "sdmmc3-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; };

ccplex@e000000 { @@ -1894,34 +1922,6 @@ cpu_bpmp_rx: sram@4f000 { }; };

- sata@3507000 { - compatible = "nvidia,tegra186-ahci"; - reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ - <0x0 0x03500000 0x0 0x00007000>, /* SATA */ - <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SATA>; - - clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, - <&bpmp TEGRA186_CLK_PLLP>; - assigned-clock-rates = <102000000>, - <204000000>; - resets = <&bpmp TEGRA186_RESET_SATA>, - <&bpmp TEGRA186_RESET_SATACOLD>; - reset-names = "sata", "sata-cold"; - status = "disabled"; - }; - bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, @@ -2052,14 +2052,7 @@ L2_A57: l2-cache1 { }; };

- pmu_denver { - compatible = "nvidia,denver-pmu"; - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&denver_0 &denver_1>; - }; - - pmu_a57 { + pmu-a57 { compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, @@ -2068,6 +2061,13 @@ pmu_a57 { interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; };

+ pmu-denver { + compatible = "nvidia,denver-pmu"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&denver_0 &denver_1>; + }; + sound { status = "disabled";

diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index cd272d407e012..5b59c1986e9b5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -147,6 +147,24 @@ pmic: pmic@3c { pinctrl-names = "default"; pinctrl-0 = <&max20024_default>;

+ fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max20024_default: pinmux { gpio0 { pins = "gpio0"; @@ -190,24 +208,6 @@ gpio7 { }; };

- fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index f018fc4c0f707..64a3398fe7a6d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -14,874 +14,830 @@ bus@0 { aconnect@2900000 { status = "okay";

- dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - ahub@2900800 { status = "okay";

- ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; - - port@7 { - reg = <0x7>; + i2s@2901000 { + status = "okay";

- xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@8 { - reg = <0x8>; + port@0 { + reg = <0>;

- xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; }; - };

- port@9 { - reg = <0x9>; + i2s1_port: port@1 { + reg = <1>;

- xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5658_ep>; + }; }; }; + };

- port@a { - reg = <0xa>; + i2s@2901100 { + status = "okay";

- xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@b { - reg = <0xb>; + port@0 { + reg = <0>;

- xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; }; - };

- port@c { - reg = <0xc>; + i2s2_port: port@1 { + reg = <1>;

- xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; }; }; + };

- port@d { - reg = <0xd>; + i2s@2901300 { + status = "okay";

- xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@e { - reg = <0xe>; + port@0 { + reg = <0>;

- xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; }; - };

- port@f { - reg = <0xf>; + i2s4_port: port@1 { + reg = <1>;

- xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; }; }; + };

- port@10 { - reg = <0x10>; + i2s@2901500 { + status = "okay";

- xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@11 { - reg = <0x11>; + port@0 { + reg = <0>;

- xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; }; - };

- port@12 { - reg = <0x12>; + i2s6_port: port@1 { + reg = <1>;

- xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; }; }; + };

- port@13 { - reg = <0x13>; + sfc@2902000 { + status = "okay";

- xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_i2s1_port: port@14 { - reg = <0x14>; + port@0 { + reg = <0>;

- xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + }; }; - };

- xbar_i2s2_port: port@15 { - reg = <0x15>; + sfc1_out_port: port@1 { + reg = <1>;

- xbar_i2s2_ep: endpoint { - remote-endpoint = <&i2s2_cif_ep>; + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + }; }; }; + };

- xbar_i2s4_port: port@17 { - reg = <0x17>; + sfc@2902200 { + status = "okay";

- xbar_i2s4_ep: endpoint { - remote-endpoint = <&i2s4_cif_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_i2s6_port: port@19 { - reg = <0x19>; + port@0 { + reg = <0>;

- xbar_i2s6_ep: endpoint { - remote-endpoint = <&i2s6_cif_ep>; + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; }; - };

- xbar_dmic3_port: port@1c { - reg = <0x1c>; + sfc2_out_port: port@1 { + reg = <1>;

- xbar_dmic3_ep: endpoint { - remote-endpoint = <&dmic3_cif_ep>; + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; }; }; + };

- xbar_sfc1_in_port: port@20 { - reg = <0x20>; + sfc@2902400 { + status = "okay";

- xbar_sfc1_in_ep: endpoint { - remote-endpoint = <&sfc1_cif_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@21 { - reg = <0x21>; + port@0 { + reg = <0>;

- xbar_sfc1_out_ep: endpoint { - remote-endpoint = <&sfc1_cif_out_ep>; + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; }; - };

- xbar_sfc2_in_port: port@22 { - reg = <0x22>; + sfc3_out_port: port@1 { + reg = <1>;

- xbar_sfc2_in_ep: endpoint { - remote-endpoint = <&sfc2_cif_in_ep>; + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; }; }; + };

- port@23 { - reg = <0x23>; + sfc@2902600 { + status = "okay";

- xbar_sfc2_out_ep: endpoint { - remote-endpoint = <&sfc2_cif_out_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_sfc3_in_port: port@24 { - reg = <0x24>; + port@0 { + reg = <0>;

- xbar_sfc3_in_ep: endpoint { - remote-endpoint = <&sfc3_cif_in_ep>; + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; }; - };

- port@25 { - reg = <0x25>; + sfc4_out_port: port@1 { + reg = <1>;

- xbar_sfc3_out_ep: endpoint { - remote-endpoint = <&sfc3_cif_out_ep>; + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; }; }; + };

- xbar_sfc4_in_port: port@26 { - reg = <0x26>; + amx@2903000 { + status = "okay";

- xbar_sfc4_in_ep: endpoint { - remote-endpoint = <&sfc4_cif_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@27 { - reg = <0x27>; + port@0 { + reg = <0>;

- xbar_sfc4_out_ep: endpoint { - remote-endpoint = <&sfc4_cif_out_ep>; + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; }; - };

- xbar_mvc1_in_port: port@28 { - reg = <0x28>; + port@1 { + reg = <1>;

- xbar_mvc1_in_ep: endpoint { - remote-endpoint = <&mvc1_cif_in_ep>; + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; }; - };

- port@29 { - reg = <0x29>; + port@2 { + reg = <2>;

- xbar_mvc1_out_ep: endpoint { - remote-endpoint = <&mvc1_cif_out_ep>; + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; }; - };

- xbar_mvc2_in_port: port@2a { - reg = <0x2a>; + port@3 { + reg = <3>;

- xbar_mvc2_in_ep: endpoint { - remote-endpoint = <&mvc2_cif_in_ep>; + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; }; - };

- port@2b { - reg = <0x2b>; + amx1_out_port: port@4 { + reg = <4>;

- xbar_mvc2_out_ep: endpoint { - remote-endpoint = <&mvc2_cif_out_ep>; + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; }; }; + };

- xbar_amx1_in1_port: port@2c { - reg = <0x2c>; + amx@2903100 { + status = "okay";

- xbar_amx1_in1_ep: endpoint { - remote-endpoint = <&amx1_in1_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx1_in2_port: port@2d { - reg = <0x2d>; + port@0 { + reg = <0>;

- xbar_amx1_in2_ep: endpoint { - remote-endpoint = <&amx1_in2_ep>; + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; }; - };

- xbar_amx1_in3_port: port@2e { - reg = <0x2e>; + port@1 { + reg = <1>;

- xbar_amx1_in3_ep: endpoint { - remote-endpoint = <&amx1_in3_ep>; + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; }; - };

- xbar_amx1_in4_port: port@2f { - reg = <0x2f>; + amx2_in3_port: port@2 { + reg = <2>;

- xbar_amx1_in4_ep: endpoint { - remote-endpoint = <&amx1_in4_ep>; + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; }; - };

- port@30 { - reg = <0x30>; + amx2_in4_port: port@3 { + reg = <3>;

- xbar_amx1_out_ep: endpoint { - remote-endpoint = <&amx1_out_ep>; + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; }; - };

- xbar_amx2_in1_port: port@31 { - reg = <0x31>; + amx2_out_port: port@4 { + reg = <4>;

- xbar_amx2_in1_ep: endpoint { - remote-endpoint = <&amx2_in1_ep>; + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; }; }; + };

- xbar_amx2_in2_port: port@32 { - reg = <0x32>; + amx@2903200 { + status = "okay";

- xbar_amx2_in2_ep: endpoint { - remote-endpoint = <&amx2_in2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx2_in3_port: port@33 { - reg = <0x33>; + port@0 { + reg = <0>;

- xbar_amx2_in3_ep: endpoint { - remote-endpoint = <&amx2_in3_ep>; + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; }; - };

- xbar_amx2_in4_port: port@34 { - reg = <0x34>; + port@1 { + reg = <1>;

- xbar_amx2_in4_ep: endpoint { - remote-endpoint = <&amx2_in4_ep>; + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; }; - };

- port@35 { - reg = <0x35>; + port@2 { + reg = <2>;

- xbar_amx2_out_ep: endpoint { - remote-endpoint = <&amx2_out_ep>; + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; }; - };

- xbar_amx3_in1_port: port@36 { - reg = <0x36>; + port@3 { + reg = <3>;

- xbar_amx3_in1_ep: endpoint { - remote-endpoint = <&amx3_in1_ep>; + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; }; - };

- xbar_amx3_in2_port: port@37 { - reg = <0x37>; + amx3_out_port: port@4 { + reg = <4>;

- xbar_amx3_in2_ep: endpoint { - remote-endpoint = <&amx3_in2_ep>; + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; }; }; + };

- xbar_amx3_in3_port: port@38 { - reg = <0x38>; + amx@2903300 { + status = "okay";

- xbar_amx3_in3_ep: endpoint { - remote-endpoint = <&amx3_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx3_in4_port: port@39 { - reg = <0x39>; + port@0 { + reg = <0>;

- xbar_amx3_in4_ep: endpoint { - remote-endpoint = <&amx3_in4_ep>; + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; }; - };

- port@3a { - reg = <0x3a>; + port@1 { + reg = <1>;

- xbar_amx3_out_ep: endpoint { - remote-endpoint = <&amx3_out_ep>; + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; }; - };

- xbar_amx4_in1_port: port@3b { - reg = <0x3b>; + port@2 { + reg = <2>;

- xbar_amx4_in1_ep: endpoint { - remote-endpoint = <&amx4_in1_ep>; + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; }; - };

- xbar_amx4_in2_port: port@3c { - reg = <0x3c>; + port@3 { + reg = <3>;

- xbar_amx4_in2_ep: endpoint { - remote-endpoint = <&amx4_in2_ep>; + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; }; - };

- xbar_amx4_in3_port: port@3d { - reg = <0x3d>; + amx4_out_port: port@4 { + reg = <4>;

- xbar_amx4_in3_ep: endpoint { - remote-endpoint = <&amx4_in3_ep>; + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; }; }; + };

- xbar_amx4_in4_port: port@3e { - reg = <0x3e>; + adx@2903800 { + status = "okay";

- xbar_amx4_in4_ep: endpoint { - remote-endpoint = <&amx4_in4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@3f { - reg = <0x3f>; + port@0 { + reg = <0>;

- xbar_amx4_out_ep: endpoint { - remote-endpoint = <&amx4_out_ep>; + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; }; - };

- xbar_adx1_in_port: port@40 { - reg = <0x40>; + adx1_out1_port: port@1 { + reg = <1>;

- xbar_adx1_in_ep: endpoint { - remote-endpoint = <&adx1_in_ep>; + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; }; - };

- port@41 { - reg = <0x41>; + adx1_out2_port: port@2 { + reg = <2>;

- xbar_adx1_out1_ep: endpoint { - remote-endpoint = <&adx1_out1_ep>; + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; }; - };

- port@42 { - reg = <0x42>; + adx1_out3_port: port@3 { + reg = <3>;

- xbar_adx1_out2_ep: endpoint { - remote-endpoint = <&adx1_out2_ep>; + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; }; - };

- port@43 { - reg = <0x43>; + adx1_out4_port: port@4 { + reg = <4>;

- xbar_adx1_out3_ep: endpoint { - remote-endpoint = <&adx1_out3_ep>; + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; }; }; + };

- port@44 { - reg = <0x44>; + adx@2903900 { + status = "okay";

- xbar_adx1_out4_ep: endpoint { - remote-endpoint = <&adx1_out4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_adx2_in_port: port@45 { - reg = <0x45>; + port@0 { + reg = <0>;

- xbar_adx2_in_ep: endpoint { - remote-endpoint = <&adx2_in_ep>; + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; }; - };

- port@46 { - reg = <0x46>; + adx2_out1_port: port@1 { + reg = <1>;

- xbar_adx2_out1_ep: endpoint { - remote-endpoint = <&adx2_out1_ep>; + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; }; - };

- port@47 { - reg = <0x47>; + adx2_out2_port: port@2 { + reg = <2>;

- xbar_adx2_out2_ep: endpoint { - remote-endpoint = <&adx2_out2_ep>; + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; }; - };

- port@48 { - reg = <0x48>; + adx2_out3_port: port@3 { + reg = <3>;

- xbar_adx2_out3_ep: endpoint { - remote-endpoint = <&adx2_out3_ep>; + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; }; - };

- port@49 { - reg = <0x49>; + adx2_out4_port: port@4 { + reg = <4>;

- xbar_adx2_out4_ep: endpoint { - remote-endpoint = <&adx2_out4_ep>; + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; }; }; + };

- xbar_adx3_in_port: port@4a { - reg = <0x4a>; + adx@2903a00 { + status = "okay";

- xbar_adx3_in_ep: endpoint { - remote-endpoint = <&adx3_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4b { - reg = <0x4b>; + port@0 { + reg = <0>;

- xbar_adx3_out1_ep: endpoint { - remote-endpoint = <&adx3_out1_ep>; + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; }; - };

- port@4c { - reg = <0x4c>; + adx3_out1_port: port@1 { + reg = <1>;

- xbar_adx3_out2_ep: endpoint { - remote-endpoint = <&adx3_out2_ep>; + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; }; - };

- port@4d { - reg = <0x4d>; + adx3_out2_port: port@2 { + reg = <2>;

- xbar_adx3_out3_ep: endpoint { - remote-endpoint = <&adx3_out3_ep>; + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; }; - };

- port@4e { - reg = <0x4e>; + adx3_out3_port: port@3 { + reg = <3>;

- xbar_adx3_out4_ep: endpoint { - remote-endpoint = <&adx3_out4_ep>; + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; }; - };

- xbar_adx4_in_port: port@4f { - reg = <0x4f>; + adx3_out4_port: port@4 { + reg = <4>;

- xbar_adx4_in_ep: endpoint { - remote-endpoint = <&adx4_in_ep>; + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; }; }; + };

- port@50 { - reg = <0x50>; + adx@2903b00 { + status = "okay";

- xbar_adx4_out1_ep: endpoint { - remote-endpoint = <&adx4_out1_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@51 { - reg = <0x51>; + port@0 { + reg = <0>;

- xbar_adx4_out2_ep: endpoint { - remote-endpoint = <&adx4_out2_ep>; + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; }; - };

- port@52 { - reg = <0x52>; + adx4_out1_port: port@1 { + reg = <1>;

- xbar_adx4_out3_ep: endpoint { - remote-endpoint = <&adx4_out3_ep>; + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; }; - };

- port@53 { - reg = <0x53>; + adx4_out2_port: port@2 { + reg = <2>;

- xbar_adx4_out4_ep: endpoint { - remote-endpoint = <&adx4_out4_ep>; + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; }; - };

- xbar_mixer_in1_port: port@54 { - reg = <0x54>; + adx4_out3_port: port@3 { + reg = <3>;

- xbar_mixer_in1_ep: endpoint { - remote-endpoint = <&mixer_in1_ep>; + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; }; - };

- xbar_mixer_in2_port: port@55 { - reg = <0x55>; + adx4_out4_port: port@4 { + reg = <4>;

- xbar_mixer_in2_ep: endpoint { - remote-endpoint = <&mixer_in2_ep>; + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; }; }; + };

- xbar_mixer_in3_port: port@56 { - reg = <0x56>; + dmic@2904200 { + status = "okay";

- xbar_mixer_in3_ep: endpoint { - remote-endpoint = <&mixer_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in4_port: port@57 { - reg = <0x57>; + port@0 { + reg = <0>;

- xbar_mixer_in4_ep: endpoint { - remote-endpoint = <&mixer_in4_ep>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; }; - };

- xbar_mixer_in5_port: port@58 { - reg = <0x58>; + dmic3_port: port@1 { + reg = <1>;

- xbar_mixer_in5_ep: endpoint { - remote-endpoint = <&mixer_in5_ep>; + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- xbar_mixer_in6_port: port@59 { - reg = <0x59>; + processing-engine@2908000 { + status = "okay";

- xbar_mixer_in6_ep: endpoint { - remote-endpoint = <&mixer_in6_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in7_port: port@5a { - reg = <0x5a>; + port@0 { + reg = <0x0>;

- xbar_mixer_in7_ep: endpoint { - remote-endpoint = <&mixer_in7_ep>; + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; }; - };

- xbar_mixer_in8_port: port@5b { - reg = <0x5b>; + ope1_out_port: port@1 { + reg = <0x1>;

- xbar_mixer_in8_ep: endpoint { - remote-endpoint = <&mixer_in8_ep>; + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; }; }; + };

- xbar_mixer_in9_port: port@5c { - reg = <0x5c>; + mvc@290a000 { + status = "okay";

- xbar_mixer_in9_ep: endpoint { - remote-endpoint = <&mixer_in9_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in10_port: port@5d { - reg = <0x5d>; + port@0 { + reg = <0>;

- xbar_mixer_in10_ep: endpoint { - remote-endpoint = <&mixer_in10_ep>; + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; }; - };

- port@5e { - reg = <0x5e>; + mvc1_out_port: port@1 { + reg = <1>;

- xbar_mixer_out1_ep: endpoint { - remote-endpoint = <&mixer_out1_ep>; + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; }; }; + };

- port@5f { - reg = <0x5f>; + mvc@290a200 { + status = "okay";

- xbar_mixer_out2_ep: endpoint { - remote-endpoint = <&mixer_out2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@60 { - reg = <0x60>; + port@0 { + reg = <0>;

- xbar_mixer_out3_ep: endpoint { - remote-endpoint = <&mixer_out3_ep>; + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; }; - };

- port@61 { - reg = <0x61>; + mvc2_out_port: port@1 { + reg = <1>;

- xbar_mixer_out4_ep: endpoint { - remote-endpoint = <&mixer_out4_ep>; + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; }; }; + };

- port@62 { - reg = <0x62>; + amixer@290bb00 { + status = "okay";

- xbar_mixer_out5_ep: endpoint { - remote-endpoint = <&mixer_out5_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_asrc_in1_port: port@63 { - reg = <0x63>; + port@0 { + reg = <0x0>;

- xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; }; - };

- port@64 { - reg = <0x64>; + port@1 { + reg = <0x1>;

- xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; }; - };

- xbar_asrc_in2_port: port@65 { - reg = <0x65>; + port@2 { + reg = <0x2>;

- xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; }; - };

- port@66 { - reg = <0x66>; + port@3 { + reg = <0x3>;

- xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; }; - };

- xbar_asrc_in3_port: port@67 { - reg = <0x67>; + port@4 { + reg = <0x4>;

- xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; }; - };

- port@68 { - reg = <0x68>; + port@5 { + reg = <0x5>;

- xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; }; - };

- xbar_asrc_in4_port: port@69 { - reg = <0x69>; + port@6 { + reg = <0x6>;

- xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; }; - };

- port@6a { - reg = <0x6a>; + port@7 { + reg = <0x7>;

- xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; }; - };

- xbar_asrc_in5_port: port@6b { - reg = <0x6b>; + port@8 { + reg = <0x8>;

- xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; }; - };

- port@6c { - reg = <0x6c>; + port@9 { + reg = <0x9>;

- xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; }; - };

- xbar_asrc_in6_port: port@6d { - reg = <0x6d>; + mixer_out1_port: port@a { + reg = <0xa>;

- xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; }; - };

- port@6e { - reg = <0x6e>; + mixer_out2_port: port@b { + reg = <0xb>;

- xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; }; - };

- xbar_asrc_in7_port: port@6f { - reg = <0x6f>; + mixer_out3_port: port@c { + reg = <0xc>;

- xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; }; - };

- xbar_ope1_in_port: port@70 { - reg = <0x70>; + mixer_out4_port: port@d { + reg = <0xd>;

- xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; }; - };

- port@71 { - reg = <0x71>; + mixer_out5_port: port@e { + reg = <0xe>;

- xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; }; }; }; @@ -1055,7 +1011,7 @@ admaif19_ep: endpoint { }; };

- i2s@2901000 { + asrc@2910000 { status = "okay";

ports { @@ -1063,936 +1019,980 @@ ports { #size-cells = <0>;

port@0 { - reg = <0>; + reg = <0x0>;

- i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; }; };

- i2s1_port: port@1 { - reg = <1>; + port@1 { + reg = <0x1>;

- i2s1_dap_ep: endpoint { - dai-format = "i2s"; - remote-endpoint = <&rt5658_ep>; + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; }; }; - }; - };

- i2s@2901100 { - status = "okay"; + port@2 { + reg = <0x2>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + };

- port@0 { - reg = <0>; + port@3 { + reg = <0x3>;

- i2s2_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s2_ep>; + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; }; };

- i2s2_port: port@1 { - reg = <1>; + port@4 { + reg = <0x4>;

- i2s2_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; }; }; - }; - };

- i2s@2901300 { - status = "okay"; + port@5 { + reg = <0x5>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + };

- port@0 { - reg = <0>; + port@6 { + reg = <0x6>;

- i2s4_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s4_ep>; + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; }; };

- i2s4_port: port@1 { - reg = <1>; + asrc_out1_port: port@7 { + reg = <0x7>;

- i2s4_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; }; }; - }; - };

- i2s@2901500 { - status = "okay"; + asrc_out2_port: port@8 { + reg = <0x8>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + };

- port@0 { - reg = <0>; + asrc_out3_port: port@9 { + reg = <0x9>;

- i2s6_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s6_ep>; + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; }; };

- i2s6_port: port@1 { - reg = <1>; + asrc_out4_port: port@a { + reg = <0xa>;

- i2s6_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; }; }; }; };

- dmic@2904200 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + port@0 { + reg = <0x0>;

- port@0 { - reg = <0>; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + };

- dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; }; + };

- dmic3_port: port@1 { - reg = <1>; + port@2 { + reg = <0x2>;

- dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; }; }; - };

- sfc@2902000 { - status = "okay"; + port@3 { + reg = <0x3>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + };

- port@0 { - reg = <0>; + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>;

- sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - }; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; }; + };

- sfc1_out_port: port@1 { - reg = <1>; + port@9 { + reg = <0x9>;

- sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - }; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; }; }; - };

- sfc@2902200 { - status = "okay"; + port@a { + reg = <0xa>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + };

- port@0 { - reg = <0>; + port@b { + reg = <0xb>;

- sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; }; + };

- sfc2_out_port: port@1 { - reg = <1>; + port@c { + reg = <0xc>;

- sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; }; }; - };

- sfc@2902400 { - status = "okay"; + port@d { + reg = <0xd>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + };

- port@0 { - reg = <0>; + port@e { + reg = <0xe>;

- sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; }; + };

- sfc3_out_port: port@1 { - reg = <1>; + port@f { + reg = <0xf>;

- sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; }; }; - };

- sfc@2902600 { - status = "okay"; + port@10 { + reg = <0x10>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + };

- port@0 { - reg = <0>; + port@11 { + reg = <0x11>;

- sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; }; + };

- sfc4_out_port: port@1 { - reg = <1>; + port@12 { + reg = <0x12>;

- sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; }; }; - };

- mvc@290a000 { - status = "okay"; + port@13 { + reg = <0x13>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_i2s1_port: port@14 { + reg = <0x14>;

- mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; }; + };

- mvc1_out_port: port@1 { - reg = <1>; + xbar_i2s2_port: port@15 { + reg = <0x15>;

- mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; }; }; - };

- mvc@290a200 { - status = "okay"; + xbar_i2s4_port: port@17 { + reg = <0x17>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_i2s6_port: port@19 { + reg = <0x19>;

- mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; }; + };

- mvc2_out_port: port@1 { - reg = <1>; + xbar_dmic3_port: port@1c { + reg = <0x1c>;

- mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; }; }; - };

- amx@2903000 { - status = "okay"; + xbar_sfc1_in_port: port@20 { + reg = <0x20>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_sfc1_in_ep: endpoint { + remote-endpoint = <&sfc1_cif_in_ep>; + }; + };

- port@0 { - reg = <0>; + port@21 { + reg = <0x21>;

- amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; + xbar_sfc1_out_ep: endpoint { + remote-endpoint = <&sfc1_cif_out_ep>; }; + };

- port@1 { - reg = <1>; + xbar_sfc2_in_port: port@22 { + reg = <0x22>;

- amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; + xbar_sfc2_in_ep: endpoint { + remote-endpoint = <&sfc2_cif_in_ep>; }; + };

- port@2 { - reg = <2>; + port@23 { + reg = <0x23>;

- amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; + xbar_sfc2_out_ep: endpoint { + remote-endpoint = <&sfc2_cif_out_ep>; }; + };

- port@3 { - reg = <3>; + xbar_sfc3_in_port: port@24 { + reg = <0x24>;

- amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; + xbar_sfc3_in_ep: endpoint { + remote-endpoint = <&sfc3_cif_in_ep>; }; + };

- amx1_out_port: port@4 { - reg = <4>; + port@25 { + reg = <0x25>;

- amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; + xbar_sfc3_out_ep: endpoint { + remote-endpoint = <&sfc3_cif_out_ep>; }; }; - };

- amx@2903100 { - status = "okay"; + xbar_sfc4_in_port: port@26 { + reg = <0x26>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_sfc4_in_ep: endpoint { + remote-endpoint = <&sfc4_cif_in_ep>; + }; + };

- port@0 { - reg = <0>; + port@27 { + reg = <0x27>;

- amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; + xbar_sfc4_out_ep: endpoint { + remote-endpoint = <&sfc4_cif_out_ep>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in_ep: endpoint { + remote-endpoint = <&mvc1_cif_in_ep>; }; + };

- port@1 { - reg = <1>; + port@29 { + reg = <0x29>;

- amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; + xbar_mvc1_out_ep: endpoint { + remote-endpoint = <&mvc1_cif_out_ep>; }; + };

- amx2_in3_port: port@2 { - reg = <2>; + xbar_mvc2_in_port: port@2a { + reg = <0x2a>;

- amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; + xbar_mvc2_in_ep: endpoint { + remote-endpoint = <&mvc2_cif_in_ep>; }; + };

- amx2_in4_port: port@3 { - reg = <3>; + port@2b { + reg = <0x2b>;

- amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; + xbar_mvc2_out_ep: endpoint { + remote-endpoint = <&mvc2_cif_out_ep>; }; + };

- amx2_out_port: port@4 { - reg = <4>; + xbar_amx1_in1_port: port@2c { + reg = <0x2c>;

- amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; + xbar_amx1_in1_ep: endpoint { + remote-endpoint = <&amx1_in1_ep>; }; }; - };

- amx@2903200 { - status = "okay"; + xbar_amx1_in2_port: port@2d { + reg = <0x2d>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx1_in2_ep: endpoint { + remote-endpoint = <&amx1_in2_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx1_in3_port: port@2e { + reg = <0x2e>;

- amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; + xbar_amx1_in3_ep: endpoint { + remote-endpoint = <&amx1_in3_ep>; }; + };

- port@1 { - reg = <1>; + xbar_amx1_in4_port: port@2f { + reg = <0x2f>;

- amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; + xbar_amx1_in4_ep: endpoint { + remote-endpoint = <&amx1_in4_ep>; }; + };

- port@2 { - reg = <2>; + port@30 { + reg = <0x30>;

- amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; + xbar_amx1_out_ep: endpoint { + remote-endpoint = <&amx1_out_ep>; }; + };

- port@3 { - reg = <3>; + xbar_amx2_in1_port: port@31 { + reg = <0x31>;

- amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; + xbar_amx2_in1_ep: endpoint { + remote-endpoint = <&amx2_in1_ep>; }; + };

- amx3_out_port: port@4 { - reg = <4>; + xbar_amx2_in2_port: port@32 { + reg = <0x32>;

- amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; + xbar_amx2_in2_ep: endpoint { + remote-endpoint = <&amx2_in2_ep>; }; }; - };

- amx@2903300 { - status = "okay"; + xbar_amx2_in3_port: port@33 { + reg = <0x33>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx2_in3_ep: endpoint { + remote-endpoint = <&amx2_in3_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx2_in4_port: port@34 { + reg = <0x34>;

- amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; + xbar_amx2_in4_ep: endpoint { + remote-endpoint = <&amx2_in4_ep>; }; + };

- port@1 { - reg = <1>; + port@35 { + reg = <0x35>;

- amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; + xbar_amx2_out_ep: endpoint { + remote-endpoint = <&amx2_out_ep>; }; + };

- port@2 { - reg = <2>; + xbar_amx3_in1_port: port@36 { + reg = <0x36>;

- amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; + xbar_amx3_in1_ep: endpoint { + remote-endpoint = <&amx3_in1_ep>; }; + };

- port@3 { - reg = <3>; + xbar_amx3_in2_port: port@37 { + reg = <0x37>;

- amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; + xbar_amx3_in2_ep: endpoint { + remote-endpoint = <&amx3_in2_ep>; }; + };

- amx4_out_port: port@4 { - reg = <4>; + xbar_amx3_in3_port: port@38 { + reg = <0x38>;

- amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; + xbar_amx3_in3_ep: endpoint { + remote-endpoint = <&amx3_in3_ep>; }; }; - };

- adx@2903800 { - status = "okay"; + xbar_amx3_in4_port: port@39 { + reg = <0x39>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx3_in4_ep: endpoint { + remote-endpoint = <&amx3_in4_ep>; + }; + };

- port@0 { - reg = <0>; + port@3a { + reg = <0x3a>;

- adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; + xbar_amx3_out_ep: endpoint { + remote-endpoint = <&amx3_out_ep>; }; + };

- adx1_out1_port: port@1 { - reg = <1>; + xbar_amx4_in1_port: port@3b { + reg = <0x3b>;

- adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; + xbar_amx4_in1_ep: endpoint { + remote-endpoint = <&amx4_in1_ep>; }; + };

- adx1_out2_port: port@2 { - reg = <2>; + xbar_amx4_in2_port: port@3c { + reg = <0x3c>;

- adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; + xbar_amx4_in2_ep: endpoint { + remote-endpoint = <&amx4_in2_ep>; }; + };

- adx1_out3_port: port@3 { - reg = <3>; + xbar_amx4_in3_port: port@3d { + reg = <0x3d>;

- adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; + xbar_amx4_in3_ep: endpoint { + remote-endpoint = <&amx4_in3_ep>; }; + };

- adx1_out4_port: port@4 { - reg = <4>; + xbar_amx4_in4_port: port@3e { + reg = <0x3e>;

- adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; + xbar_amx4_in4_ep: endpoint { + remote-endpoint = <&amx4_in4_ep>; }; }; - };

- adx@2903900 { - status = "okay"; + port@3f { + reg = <0x3f>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx4_out_ep: endpoint { + remote-endpoint = <&amx4_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_adx1_in_port: port@40 { + reg = <0x40>;

- adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; + xbar_adx1_in_ep: endpoint { + remote-endpoint = <&adx1_in_ep>; }; + };

- adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; + port@41 { + reg = <0x41>; + + xbar_adx1_out1_ep: endpoint { + remote-endpoint = <&adx1_out1_ep>; }; + };

- adx2_out2_port: port@2 { - reg = <2>; + port@42 { + reg = <0x42>;

- adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; + xbar_adx1_out2_ep: endpoint { + remote-endpoint = <&adx1_out2_ep>; }; + };

- adx2_out3_port: port@3 { - reg = <3>; + port@43 { + reg = <0x43>;

- adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; + xbar_adx1_out3_ep: endpoint { + remote-endpoint = <&adx1_out3_ep>; }; + };

- adx2_out4_port: port@4 { - reg = <4>; + port@44 { + reg = <0x44>;

- adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; + xbar_adx1_out4_ep: endpoint { + remote-endpoint = <&adx1_out4_ep>; }; }; - };

- adx@2903a00 { - status = "okay"; + xbar_adx2_in_port: port@45 { + reg = <0x45>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx2_in_ep: endpoint { + remote-endpoint = <&adx2_in_ep>; + }; + };

- port@0 { - reg = <0>; + port@46 { + reg = <0x46>;

- adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; + xbar_adx2_out1_ep: endpoint { + remote-endpoint = <&adx2_out1_ep>; }; + };

- adx3_out1_port: port@1 { - reg = <1>; + port@47 { + reg = <0x47>;

- adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; + xbar_adx2_out2_ep: endpoint { + remote-endpoint = <&adx2_out2_ep>; }; + };

- adx3_out2_port: port@2 { - reg = <2>; + port@48 { + reg = <0x48>;

- adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; + xbar_adx2_out3_ep: endpoint { + remote-endpoint = <&adx2_out3_ep>; }; + };

- adx3_out3_port: port@3 { - reg = <3>; + port@49 { + reg = <0x49>;

- adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; + xbar_adx2_out4_ep: endpoint { + remote-endpoint = <&adx2_out4_ep>; }; + };

- adx3_out4_port: port@4 { - reg = <4>; + xbar_adx3_in_port: port@4a { + reg = <0x4a>;

- adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; + xbar_adx3_in_ep: endpoint { + remote-endpoint = <&adx3_in_ep>; }; }; - };

- adx@2903b00 { - status = "okay"; + port@4b { + reg = <0x4b>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx3_out1_ep: endpoint { + remote-endpoint = <&adx3_out1_ep>; + }; + };

- port@0 { - reg = <0>; + port@4c { + reg = <0x4c>;

- adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; + xbar_adx3_out2_ep: endpoint { + remote-endpoint = <&adx3_out2_ep>; }; + };

- adx4_out1_port: port@1 { - reg = <1>; + port@4d { + reg = <0x4d>;

- adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; + xbar_adx3_out3_ep: endpoint { + remote-endpoint = <&adx3_out3_ep>; }; + };

- adx4_out2_port: port@2 { - reg = <2>; + port@4e { + reg = <0x4e>;

- adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; + xbar_adx3_out4_ep: endpoint { + remote-endpoint = <&adx3_out4_ep>; }; + };

- adx4_out3_port: port@3 { - reg = <3>; + xbar_adx4_in_port: port@4f { + reg = <0x4f>;

- adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; + xbar_adx4_in_ep: endpoint { + remote-endpoint = <&adx4_in_ep>; }; + };

- adx4_out4_port: port@4 { - reg = <4>; + port@50 { + reg = <0x50>;

- adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; + xbar_adx4_out1_ep: endpoint { + remote-endpoint = <&adx4_out1_ep>; }; }; - };

- processing-engine@2908000 { - status = "okay"; + port@51 { + reg = <0x51>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx4_out2_ep: endpoint { + remote-endpoint = <&adx4_out2_ep>; + }; + };

- port@0 { - reg = <0x0>; + port@52 { + reg = <0x52>;

- ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; + xbar_adx4_out3_ep: endpoint { + remote-endpoint = <&adx4_out3_ep>; }; + };

- ope1_out_port: port@1 { - reg = <0x1>; + port@53 { + reg = <0x53>;

- ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; + xbar_adx4_out4_ep: endpoint { + remote-endpoint = <&adx4_out4_ep>; }; }; - };

- amixer@290bb00 { - status = "okay"; + xbar_mixer_in1_port: port@54 { + reg = <0x54>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_mixer_in1_ep: endpoint { + remote-endpoint = <&mixer_in1_ep>; + }; + };

- port@0 { - reg = <0x0>; + xbar_mixer_in2_port: port@55 { + reg = <0x55>;

- mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; + xbar_mixer_in2_ep: endpoint { + remote-endpoint = <&mixer_in2_ep>; }; + };

- port@1 { - reg = <0x1>; + xbar_mixer_in3_port: port@56 { + reg = <0x56>;

- mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; + xbar_mixer_in3_ep: endpoint { + remote-endpoint = <&mixer_in3_ep>; }; + };

- port@2 { - reg = <0x2>; + xbar_mixer_in4_port: port@57 { + reg = <0x57>;

- mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; + xbar_mixer_in4_ep: endpoint { + remote-endpoint = <&mixer_in4_ep>; }; + };

- port@3 { - reg = <0x3>; + xbar_mixer_in5_port: port@58 { + reg = <0x58>;

- mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; + xbar_mixer_in5_ep: endpoint { + remote-endpoint = <&mixer_in5_ep>; }; + };

- port@4 { - reg = <0x4>; + xbar_mixer_in6_port: port@59 { + reg = <0x59>;

- mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; + xbar_mixer_in6_ep: endpoint { + remote-endpoint = <&mixer_in6_ep>; }; + };

- port@5 { - reg = <0x5>; + xbar_mixer_in7_port: port@5a { + reg = <0x5a>;

- mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; + xbar_mixer_in7_ep: endpoint { + remote-endpoint = <&mixer_in7_ep>; }; + };

- port@6 { - reg = <0x6>; + xbar_mixer_in8_port: port@5b { + reg = <0x5b>;

- mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; + xbar_mixer_in8_ep: endpoint { + remote-endpoint = <&mixer_in8_ep>; }; + };

- port@7 { - reg = <0x7>; + xbar_mixer_in9_port: port@5c { + reg = <0x5c>;

- mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; + xbar_mixer_in9_ep: endpoint { + remote-endpoint = <&mixer_in9_ep>; }; + };

- port@8 { - reg = <0x8>; + xbar_mixer_in10_port: port@5d { + reg = <0x5d>;

- mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; + xbar_mixer_in10_ep: endpoint { + remote-endpoint = <&mixer_in10_ep>; }; + };

- port@9 { - reg = <0x9>; + port@5e { + reg = <0x5e>;

- mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; + xbar_mixer_out1_ep: endpoint { + remote-endpoint = <&mixer_out1_ep>; }; + };

- mixer_out1_port: port@a { - reg = <0xa>; + port@5f { + reg = <0x5f>;

- mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; + xbar_mixer_out2_ep: endpoint { + remote-endpoint = <&mixer_out2_ep>; }; + };

- mixer_out2_port: port@b { - reg = <0xb>; + port@60 { + reg = <0x60>;

- mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; + xbar_mixer_out3_ep: endpoint { + remote-endpoint = <&mixer_out3_ep>; }; + };

- mixer_out3_port: port@c { - reg = <0xc>; + port@61 { + reg = <0x61>;

- mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; + xbar_mixer_out4_ep: endpoint { + remote-endpoint = <&mixer_out4_ep>; }; + };

- mixer_out4_port: port@d { - reg = <0xd>; + port@62 { + reg = <0x62>;

- mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; + xbar_mixer_out5_ep: endpoint { + remote-endpoint = <&mixer_out5_ep>; }; + };

- mixer_out5_port: port@e { - reg = <0xe>; + xbar_asrc_in1_port: port@63 { + reg = <0x63>;

- mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; }; }; - };

- asrc@2910000 { - status = "okay"; + port@64 { + reg = <0x64>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + };

- port@0 { - reg = <0x0>; + xbar_asrc_in2_port: port@65 { + reg = <0x65>;

- asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; }; + };

- port@1 { - reg = <0x1>; + port@66 { + reg = <0x66>;

- asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; }; + };

- port@2 { - reg = <0x2>; + xbar_asrc_in3_port: port@67 { + reg = <0x67>;

- asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; }; + };

- port@3 { - reg = <0x3>; + port@68 { + reg = <0x68>;

- asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; }; + };

- port@4 { - reg = <0x4>; + xbar_asrc_in4_port: port@69 { + reg = <0x69>;

- asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; }; + };

- port@5 { - reg = <0x5>; + port@6a { + reg = <0x6a>;

- asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; }; + };

- port@6 { - reg = <0x6>; + xbar_asrc_in5_port: port@6b { + reg = <0x6b>;

- asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; }; + };

- asrc_out1_port: port@7 { - reg = <0x7>; + port@6c { + reg = <0x6c>;

- asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; }; + };

- asrc_out2_port: port@8 { - reg = <0x8>; + xbar_asrc_in6_port: port@6d { + reg = <0x6d>;

- asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; }; + };

- asrc_out3_port: port@9 { - reg = <0x9>; + port@6e { + reg = <0x6e>;

- asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; }; + };

- asrc_out4_port: port@a { - reg = <0xa>; + xbar_asrc_in7_port: port@6f { + reg = <0x6f>;

- asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; }; + };

- asrc_out5_port: port@b { - reg = <0xb>; + xbar_ope1_in_port: port@70 { + reg = <0x70>;

- asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; }; + };

- asrc_out6_port: port@c { - reg = <0xc>; + port@71 { + reg = <0x71>;

- asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; }; }; }; }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; };

i2c@3160000 { @@ -2247,14 +2247,6 @@ pcie-ep@141a0000 { }; };

- fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - gpio-keys { compatible = "gpio-keys";

@@ -2279,6 +2271,14 @@ key-power { }; };

+ fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + sound { compatible = "nvidia,tegra186-audio-graph-card"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 617fbfaaf02f6..4a17ea5e40fd0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0

+#include <dt-bindings/gpio/tegra194-gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h>

@@ -8,890 +9,880 @@ bus@0 { aconnect@2900000 { status = "okay";

- dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - ahub@2900800 { status = "okay";

- ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; + i2s@2901200 { + status = "okay";

- xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4 { - reg = <0x4>; + port@0 { + reg = <0>;

- xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; }; - };

- port@5 { - reg = <0x5>; + i2s3_port: port@1 { + reg = <1>;

- xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; }; }; + };

- port@6 { - reg = <0x6>; + i2s@2901400 { + status = "okay";

- xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@7 { - reg = <0x7>; + port@0 { + reg = <0>;

- xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; }; - };

- port@8 { - reg = <0x8>; + i2s5_port: port@1 { + reg = <1>;

- xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; }; }; + };

- port@9 { - reg = <0x9>; + sfc@2902000 { + status = "okay";

- xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@a { - reg = <0xa>; + port@0 { + reg = <0>;

- xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + convert-rate = <44100>; + }; }; - };

- port@b { - reg = <0xb>; + sfc1_out_port: port@1 { + reg = <1>;

- xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + convert-rate = <48000>; + }; }; }; + };

- port@c { - reg = <0xc>; + sfc@2902200 { + status = "okay";

- xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@d { - reg = <0xd>; + port@0 { + reg = <0>;

- xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; }; - };

- port@e { - reg = <0xe>; + sfc2_out_port: port@1 { + reg = <1>;

- xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; }; }; + };

- port@f { - reg = <0xf>; + sfc@2902400 { + status = "okay";

- xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@10 { - reg = <0x10>; + port@0 { + reg = <0>;

- xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; }; - };

- port@11 { - reg = <0x11>; + sfc3_out_port: port@1 { + reg = <1>;

- xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; }; }; + };

- port@12 { - reg = <0x12>; + sfc@2902600 { + status = "okay";

- xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@13 { - reg = <0x13>; + port@0 { + reg = <0>;

- xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; }; - };

- xbar_i2s3_port: port@16 { - reg = <0x16>; + sfc4_out_port: port@1 { + reg = <1>;

- xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; }; }; + };

- xbar_i2s5_port: port@18 { - reg = <0x18>; + amx@2903000 { + status = "okay";

- xbar_i2s5_ep: endpoint { - remote-endpoint = <&i2s5_cif_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_dmic1_port: port@1a { - reg = <0x1a>; + port@0 { + reg = <0>;

- xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; }; - };

- xbar_dmic2_port: port@1b { - reg = <0x1b>; + port@1 { + reg = <1>;

- xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; }; - };

- xbar_dmic4_port: port@1d { - reg = <0x1d>; + port@2 { + reg = <2>;

- xbar_dmic4_ep: endpoint { - remote-endpoint = <&dmic4_cif_ep>; + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; }; - };

- xbar_dspk1_port: port@1e { - reg = <0x1e>; + port@3 { + reg = <3>;

- xbar_dspk1_ep: endpoint { - remote-endpoint = <&dspk1_cif_ep>; + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; }; - };

- xbar_dspk2_port: port@1f { - reg = <0x1f>; + amx1_out_port: port@4 { + reg = <4>;

- xbar_dspk2_ep: endpoint { - remote-endpoint = <&dspk2_cif_ep>; + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; }; }; + };

- xbar_sfc1_in_port: port@20 { - reg = <0x20>; + amx@2903100 { + status = "okay";

- xbar_sfc1_in_ep: endpoint { - remote-endpoint = <&sfc1_cif_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@21 { - reg = <0x21>; + port@0 { + reg = <0>;

- xbar_sfc1_out_ep: endpoint { - remote-endpoint = <&sfc1_cif_out_ep>; + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; }; - };

- xbar_sfc2_in_port: port@22 { - reg = <0x22>; + port@1 { + reg = <1>;

- xbar_sfc2_in_ep: endpoint { - remote-endpoint = <&sfc2_cif_in_ep>; + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; }; - };

- port@23 { - reg = <0x23>; + amx2_in3_port: port@2 { + reg = <2>;

- xbar_sfc2_out_ep: endpoint { - remote-endpoint = <&sfc2_cif_out_ep>; + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; }; - };

- xbar_sfc3_in_port: port@24 { - reg = <0x24>; + amx2_in4_port: port@3 { + reg = <3>;

- xbar_sfc3_in_ep: endpoint { - remote-endpoint = <&sfc3_cif_in_ep>; + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; }; - };

- port@25 { - reg = <0x25>; + amx2_out_port: port@4 { + reg = <4>;

- xbar_sfc3_out_ep: endpoint { - remote-endpoint = <&sfc3_cif_out_ep>; + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; }; }; + };

- xbar_sfc4_in_port: port@26 { - reg = <0x26>; + amx@2903200 { + status = "okay";

- xbar_sfc4_in_ep: endpoint { - remote-endpoint = <&sfc4_cif_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@27 { - reg = <0x27>; + port@0 { + reg = <0>;

- xbar_sfc4_out_ep: endpoint { - remote-endpoint = <&sfc4_cif_out_ep>; + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; }; - };

- xbar_mvc1_in_port: port@28 { - reg = <0x28>; + port@1 { + reg = <1>;

- xbar_mvc1_in_ep: endpoint { - remote-endpoint = <&mvc1_cif_in_ep>; + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; }; - }; - - port@29 { - reg = <0x29>;

- xbar_mvc1_out_ep: endpoint { - remote-endpoint = <&mvc1_cif_out_ep>; + port@2 { + reg = <2>; + + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; }; - };

- xbar_mvc2_in_port: port@2a { - reg = <0x2a>; + port@3 { + reg = <3>;

- xbar_mvc2_in_ep: endpoint { - remote-endpoint = <&mvc2_cif_in_ep>; + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; }; - };

- port@2b { - reg = <0x2b>; + amx3_out_port: port@4 { + reg = <4>;

- xbar_mvc2_out_ep: endpoint { - remote-endpoint = <&mvc2_cif_out_ep>; + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; }; }; + };

- xbar_amx1_in1_port: port@2c { - reg = <0x2c>; + amx@2903300 { + status = "okay";

- xbar_amx1_in1_ep: endpoint { - remote-endpoint = <&amx1_in1_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx1_in2_port: port@2d { - reg = <0x2d>; + port@0 { + reg = <0>;

- xbar_amx1_in2_ep: endpoint { - remote-endpoint = <&amx1_in2_ep>; + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; }; - };

- xbar_amx1_in3_port: port@2e { - reg = <0x2e>; + port@1 { + reg = <1>;

- xbar_amx1_in3_ep: endpoint { - remote-endpoint = <&amx1_in3_ep>; + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; }; - };

- xbar_amx1_in4_port: port@2f { - reg = <0x2f>; + port@2 { + reg = <2>;

- xbar_amx1_in4_ep: endpoint { - remote-endpoint = <&amx1_in4_ep>; + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; }; - };

- port@30 { - reg = <0x30>; + port@3 { + reg = <3>;

- xbar_amx1_out_ep: endpoint { - remote-endpoint = <&amx1_out_ep>; + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; }; - };

- xbar_amx2_in1_port: port@31 { - reg = <0x31>; + amx4_out_port: port@4 { + reg = <4>;

- xbar_amx2_in1_ep: endpoint { - remote-endpoint = <&amx2_in1_ep>; + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; }; }; + };

- xbar_amx2_in2_port: port@32 { - reg = <0x32>; + adx@2903800 { + status = "okay";

- xbar_amx2_in2_ep: endpoint { - remote-endpoint = <&amx2_in2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx2_in3_port: port@33 { - reg = <0x33>; + port@0 { + reg = <0>;

- xbar_amx2_in3_ep: endpoint { - remote-endpoint = <&amx2_in3_ep>; + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; }; - };

- xbar_amx2_in4_port: port@34 { - reg = <0x34>; + adx1_out1_port: port@1 { + reg = <1>;

- xbar_amx2_in4_ep: endpoint { - remote-endpoint = <&amx2_in4_ep>; + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; }; - };

- port@35 { - reg = <0x35>; + adx1_out2_port: port@2 { + reg = <2>;

- xbar_amx2_out_ep: endpoint { - remote-endpoint = <&amx2_out_ep>; + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; }; - };

- xbar_amx3_in1_port: port@36 { - reg = <0x36>; + adx1_out3_port: port@3 { + reg = <3>;

- xbar_amx3_in1_ep: endpoint { - remote-endpoint = <&amx3_in1_ep>; + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; }; - };

- xbar_amx3_in2_port: port@37 { - reg = <0x37>; + adx1_out4_port: port@4 { + reg = <4>;

- xbar_amx3_in2_ep: endpoint { - remote-endpoint = <&amx3_in2_ep>; + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; }; }; + };

- xbar_amx3_in3_port: port@38 { - reg = <0x38>; + adx@2903900 { + status = "okay";

- xbar_amx3_in3_ep: endpoint { - remote-endpoint = <&amx3_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_amx3_in4_port: port@39 { - reg = <0x39>; + port@0 { + reg = <0>;

- xbar_amx3_in4_ep: endpoint { - remote-endpoint = <&amx3_in4_ep>; + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; }; - };

- port@3a { - reg = <0x3a>; + adx2_out1_port: port@1 { + reg = <1>;

- xbar_amx3_out_ep: endpoint { - remote-endpoint = <&amx3_out_ep>; + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; }; - };

- xbar_amx4_in1_port: port@3b { - reg = <0x3b>; + adx2_out2_port: port@2 { + reg = <2>;

- xbar_amx4_in1_ep: endpoint { - remote-endpoint = <&amx4_in1_ep>; + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; }; - };

- xbar_amx4_in2_port: port@3c { - reg = <0x3c>; + adx2_out3_port: port@3 { + reg = <3>;

- xbar_amx4_in2_ep: endpoint { - remote-endpoint = <&amx4_in2_ep>; + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; }; - };

- xbar_amx4_in3_port: port@3d { - reg = <0x3d>; + adx2_out4_port: port@4 { + reg = <4>;

- xbar_amx4_in3_ep: endpoint { - remote-endpoint = <&amx4_in3_ep>; + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; }; }; + };

- xbar_amx4_in4_port: port@3e { - reg = <0x3e>; + adx@2903a00 { + status = "okay";

- xbar_amx4_in4_ep: endpoint { - remote-endpoint = <&amx4_in4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@3f { - reg = <0x3f>; + port@0 { + reg = <0>;

- xbar_amx4_out_ep: endpoint { - remote-endpoint = <&amx4_out_ep>; + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; }; - };

- xbar_adx1_in_port: port@40 { - reg = <0x40>; + adx3_out1_port: port@1 { + reg = <1>;

- xbar_adx1_in_ep: endpoint { - remote-endpoint = <&adx1_in_ep>; + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; }; - };

- port@41 { - reg = <0x41>; + adx3_out2_port: port@2 { + reg = <2>;

- xbar_adx1_out1_ep: endpoint { - remote-endpoint = <&adx1_out1_ep>; + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; }; - };

- port@42 { - reg = <0x42>; + adx3_out3_port: port@3 { + reg = <3>;

- xbar_adx1_out2_ep: endpoint { - remote-endpoint = <&adx1_out2_ep>; + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; }; - };

- port@43 { - reg = <0x43>; + adx3_out4_port: port@4 { + reg = <4>;

- xbar_adx1_out3_ep: endpoint { - remote-endpoint = <&adx1_out3_ep>; + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; }; }; + };

- port@44 { - reg = <0x44>; + adx@2903b00 { + status = "okay";

- xbar_adx1_out4_ep: endpoint { - remote-endpoint = <&adx1_out4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_adx2_in_port: port@45 { - reg = <0x45>; + port@0 { + reg = <0>;

- xbar_adx2_in_ep: endpoint { - remote-endpoint = <&adx2_in_ep>; + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; }; - };

- port@46 { - reg = <0x46>; + adx4_out1_port: port@1 { + reg = <1>;

- xbar_adx2_out1_ep: endpoint { - remote-endpoint = <&adx2_out1_ep>; + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; }; - };

- port@47 { - reg = <0x47>; + adx4_out2_port: port@2 { + reg = <2>;

- xbar_adx2_out2_ep: endpoint { - remote-endpoint = <&adx2_out2_ep>; + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; }; - };

- port@48 { - reg = <0x48>; + adx4_out3_port: port@3 { + reg = <3>;

- xbar_adx2_out3_ep: endpoint { - remote-endpoint = <&adx2_out3_ep>; + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; }; - };

- port@49 { - reg = <0x49>; + adx4_out4_port: port@4 { + reg = <4>;

- xbar_adx2_out4_ep: endpoint { - remote-endpoint = <&adx2_out4_ep>; + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; }; }; + };

- xbar_adx3_in_port: port@4a { - reg = <0x4a>; + dmic@2904000 { + status = "okay";

- xbar_adx3_in_ep: endpoint { - remote-endpoint = <&adx3_in_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4b { - reg = <0x4b>; + port@0 { + reg = <0>;

- xbar_adx3_out1_ep: endpoint { - remote-endpoint = <&adx3_out1_ep>; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; }; - };

- port@4c { - reg = <0x4c>; + dmic1_port: port@1 { + reg = <1>;

- xbar_adx3_out2_ep: endpoint { - remote-endpoint = <&adx3_out2_ep>; + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@4d { - reg = <0x4d>; + dmic@2904100 { + status = "okay";

- xbar_adx3_out3_ep: endpoint { - remote-endpoint = <&adx3_out3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@4e { - reg = <0x4e>; + port@0 { + reg = <0>;

- xbar_adx3_out4_ep: endpoint { - remote-endpoint = <&adx3_out4_ep>; + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; }; - };

- xbar_adx4_in_port: port@4f { - reg = <0x4f>; + dmic2_port: port@1 { + reg = <1>;

- xbar_adx4_in_ep: endpoint { - remote-endpoint = <&adx4_in_ep>; + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@50 { - reg = <0x50>; + dmic@2904300 { + status = "okay";

- xbar_adx4_out1_ep: endpoint { - remote-endpoint = <&adx4_out1_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@51 { - reg = <0x51>; + port@0 { + reg = <0>;

- xbar_adx4_out2_ep: endpoint { - remote-endpoint = <&adx4_out2_ep>; + dmic4_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic4_ep>; + }; }; - };

- port@52 { - reg = <0x52>; + dmic4_port: port@1 { + reg = <1>;

- xbar_adx4_out3_ep: endpoint { - remote-endpoint = <&adx4_out3_ep>; + dmic4_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- port@53 { - reg = <0x53>; + dspk@2905000 { + status = "okay";

- xbar_adx4_out4_ep: endpoint { - remote-endpoint = <&adx4_out4_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in1_port: port@54 { - reg = <0x54>; + port@0 { + reg = <0>;

- xbar_mixer_in1_ep: endpoint { - remote-endpoint = <&mixer_in1_ep>; + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; }; - };

- xbar_mixer_in2_port: port@55 { - reg = <0x55>; + dspk1_port: port@1 { + reg = <1>;

- xbar_mixer_in2_ep: endpoint { - remote-endpoint = <&mixer_in2_ep>; + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- xbar_mixer_in3_port: port@56 { - reg = <0x56>; + dspk@2905100 { + status = "okay";

- xbar_mixer_in3_ep: endpoint { - remote-endpoint = <&mixer_in3_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in4_port: port@57 { - reg = <0x57>; + port@0 { + reg = <0>;

- xbar_mixer_in4_ep: endpoint { - remote-endpoint = <&mixer_in4_ep>; + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; }; - };

- xbar_mixer_in5_port: port@58 { - reg = <0x58>; + dspk2_port: port@1 { + reg = <1>;

- xbar_mixer_in5_ep: endpoint { - remote-endpoint = <&mixer_in5_ep>; + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; }; }; + };

- xbar_mixer_in6_port: port@59 { - reg = <0x59>; + processing-engine@2908000 { + status = "okay";

- xbar_mixer_in6_ep: endpoint { - remote-endpoint = <&mixer_in6_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in7_port: port@5a { - reg = <0x5a>; + port@0 { + reg = <0x0>;

- xbar_mixer_in7_ep: endpoint { - remote-endpoint = <&mixer_in7_ep>; + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; }; - };

- xbar_mixer_in8_port: port@5b { - reg = <0x5b>; + ope1_out_port: port@1 { + reg = <0x1>;

- xbar_mixer_in8_ep: endpoint { - remote-endpoint = <&mixer_in8_ep>; + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; }; }; + };

- xbar_mixer_in9_port: port@5c { - reg = <0x5c>; + mvc@290a000 { + status = "okay";

- xbar_mixer_in9_ep: endpoint { - remote-endpoint = <&mixer_in9_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_mixer_in10_port: port@5d { - reg = <0x5d>; + port@0 { + reg = <0>;

- xbar_mixer_in10_ep: endpoint { - remote-endpoint = <&mixer_in10_ep>; + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; }; - };

- port@5e { - reg = <0x5e>; + mvc1_out_port: port@1 { + reg = <1>;

- xbar_mixer_out1_ep: endpoint { - remote-endpoint = <&mixer_out1_ep>; + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; }; }; + };

- port@5f { - reg = <0x5f>; + mvc@290a200 { + status = "okay";

- xbar_mixer_out2_ep: endpoint { - remote-endpoint = <&mixer_out2_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@60 { - reg = <0x60>; + port@0 { + reg = <0>;

- xbar_mixer_out3_ep: endpoint { - remote-endpoint = <&mixer_out3_ep>; + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; }; - };

- port@61 { - reg = <0x61>; + mvc2_out_port: port@1 { + reg = <1>;

- xbar_mixer_out4_ep: endpoint { - remote-endpoint = <&mixer_out4_ep>; + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; }; }; + };

- port@62 { - reg = <0x62>; + amixer@290bb00 { + status = "okay";

- xbar_mixer_out5_ep: endpoint { - remote-endpoint = <&mixer_out5_ep>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- xbar_asrc_in1_port: port@63 { - reg = <0x63>; + port@0 { + reg = <0x0>;

- xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; }; - };

- port@64 { - reg = <0x64>; + port@1 { + reg = <0x1>;

- xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; }; - };

- xbar_asrc_in2_port: port@65 { - reg = <0x65>; + port@2 { + reg = <0x2>;

- xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; }; - };

- port@66 { - reg = <0x66>; + port@3 { + reg = <0x3>;

- xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; }; - };

- xbar_asrc_in3_port: port@67 { - reg = <0x67>; + port@4 { + reg = <0x4>;

- xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; }; - };

- port@68 { - reg = <0x68>; + port@5 { + reg = <0x5>;

- xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; }; - };

- xbar_asrc_in4_port: port@69 { - reg = <0x69>; + port@6 { + reg = <0x6>;

- xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; }; - };

- port@6a { - reg = <0x6a>; + port@7 { + reg = <0x7>;

- xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; }; - };

- xbar_asrc_in5_port: port@6b { - reg = <0x6b>; + port@8 { + reg = <0x8>;

- xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; }; - };

- port@6c { - reg = <0x6c>; + port@9 { + reg = <0x9>;

- xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; }; - };

- xbar_asrc_in6_port: port@6d { - reg = <0x6d>; + mixer_out1_port: port@a { + reg = <0xa>;

- xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; }; - };

- port@6e { - reg = <0x6e>; + mixer_out2_port: port@b { + reg = <0xb>;

- xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; }; - };

- xbar_asrc_in7_port: port@6f { - reg = <0x6f>; + mixer_out3_port: port@c { + reg = <0xc>;

- xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; }; - };

- xbar_ope1_in_port: port@70 { - reg = <0x70>; + mixer_out4_port: port@d { + reg = <0xd>;

- xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; }; - };

- port@71 { - reg = <0x71>; + mixer_out5_port: port@e { + reg = <0xe>;

- xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; }; }; }; @@ -1065,7 +1056,7 @@ admaif19_ep: endpoint { }; };

- i2s@2901200 { + asrc@2910000 { status = "okay";

ports { @@ -1073,990 +1064,996 @@ ports { #size-cells = <0>;

port@0 { - reg = <0>; + reg = <0x0>;

- i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; }; };

- i2s3_port: port@1 { - reg = <1>; + port@1 { + reg = <0x1>;

- i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; }; }; - }; - };

- i2s@2901400 { - status = "okay"; + port@4 { + reg = <0x4>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + };

- port@0 { - reg = <0>; + port@5 { + reg = <0x5>;

- i2s5_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s5_ep>; + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; }; };

- i2s5_port: port@1 { - reg = <1>; + port@6 { + reg = <0x6>;

- i2s5_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; }; }; - }; - };

- dmic@2904000 { - status = "okay"; + asrc_out1_port: port@7 { + reg = <0x7>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + };

- port@0 { - reg = <0>; + asrc_out2_port: port@8 { + reg = <0x8>;

- dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; }; };

- dmic1_port: port@1 { - reg = <1>; + asrc_out3_port: port@9 { + reg = <0x9>;

- dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; }; }; - }; - };

- dmic@2904100 { - status = "okay"; + asrc_out4_port: port@a { + reg = <0xa>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + };

- port@0 { - reg = <0>; + asrc_out5_port: port@b { + reg = <0xb>;

- dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; }; };

- dmic2_port: port@1 { - reg = <1>; + asrc_out6_port: port@c { + reg = <0xc>;

- dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; }; }; }; };

- dmic@2904300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>;

- port@0 { - reg = <0>; + port@0 { + reg = <0x0>;

- dmic4_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic4_ep>; - }; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; }; + };

- dmic4_port: port@1 { - reg = <1>; + port@1 { + reg = <0x1>;

- dmic4_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; }; }; - };

- dspk@2905000 { - status = "okay"; + port@2 { + reg = <0x2>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + };

- port@0 { - reg = <0>; + port@3 { + reg = <0x3>;

- dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; }; + };

- dspk1_port: port@1 { - reg = <1>; + port@4 { + reg = <0x4>;

- dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; }; }; - };

- dspk@2905100 { - status = "okay"; + port@5 { + reg = <0x5>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + };

- port@0 { - reg = <0>; + port@6 { + reg = <0x6>;

- dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; }; + };

- dspk2_port: port@1 { - reg = <1>; + port@7 { + reg = <0x7>;

- dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; }; }; - };

- sfc@2902000 { - status = "okay"; + port@8 { + reg = <0x8>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + };

- port@0 { - reg = <0>; + port@9 { + reg = <0x9>;

- sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - convert-rate = <44100>; - }; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; }; + };

- sfc1_out_port: port@1 { - reg = <1>; + port@a { + reg = <0xa>;

- sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - convert-rate = <48000>; - }; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; }; }; - };

- sfc@2902200 { - status = "okay"; + port@b { + reg = <0xb>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + };

- port@0 { - reg = <0>; + port@c { + reg = <0xc>;

- sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; }; + };

- sfc2_out_port: port@1 { - reg = <1>; + port@d { + reg = <0xd>;

- sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; }; }; - };

- sfc@2902400 { - status = "okay"; + port@e { + reg = <0xe>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + };

- port@0 { - reg = <0>; + port@f { + reg = <0xf>;

- sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; }; + };

- sfc3_out_port: port@1 { - reg = <1>; + port@10 { + reg = <0x10>;

- sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; }; }; - };

- sfc@2902600 { - status = "okay"; + port@11 { + reg = <0x11>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + };

- port@0 { - reg = <0>; + port@12 { + reg = <0x12>;

- sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; }; + };

- sfc4_out_port: port@1 { - reg = <1>; + port@13 { + reg = <0x13>;

- sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; }; }; - };

- mvc@290a000 { - status = "okay"; + xbar_i2s3_port: port@16 { + reg = <0x16>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_i2s5_port: port@18 { + reg = <0x18>;

- mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; }; + };

- mvc1_out_port: port@1 { - reg = <1>; + xbar_dmic1_port: port@1a { + reg = <0x1a>;

- mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; }; }; - };

- mvc@290a200 { - status = "okay"; + xbar_dmic2_port: port@1b { + reg = <0x1b>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_dmic4_port: port@1d { + reg = <0x1d>;

- mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; + xbar_dmic4_ep: endpoint { + remote-endpoint = <&dmic4_cif_ep>; }; + };

- mvc2_out_port: port@1 { - reg = <1>; + xbar_dspk1_port: port@1e { + reg = <0x1e>;

- mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; }; }; - };

- amx@2903000 { - status = "okay"; + xbar_dspk2_port: port@1f { + reg = <0x1f>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_sfc1_in_port: port@20 { + reg = <0x20>;

- amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; + xbar_sfc1_in_ep: endpoint { + remote-endpoint = <&sfc1_cif_in_ep>; }; + };

- port@1 { - reg = <1>; + port@21 { + reg = <0x21>;

- amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; + xbar_sfc1_out_ep: endpoint { + remote-endpoint = <&sfc1_cif_out_ep>; }; + };

- port@2 { - reg = <2>; + xbar_sfc2_in_port: port@22 { + reg = <0x22>;

- amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; + xbar_sfc2_in_ep: endpoint { + remote-endpoint = <&sfc2_cif_in_ep>; }; + };

- port@3 { - reg = <3>; + port@23 { + reg = <0x23>;

- amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; + xbar_sfc2_out_ep: endpoint { + remote-endpoint = <&sfc2_cif_out_ep>; }; + };

- amx1_out_port: port@4 { - reg = <4>; + xbar_sfc3_in_port: port@24 { + reg = <0x24>;

- amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; + xbar_sfc3_in_ep: endpoint { + remote-endpoint = <&sfc3_cif_in_ep>; }; }; - };

- amx@2903100 { - status = "okay"; + port@25 { + reg = <0x25>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_sfc3_out_ep: endpoint { + remote-endpoint = <&sfc3_cif_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_sfc4_in_port: port@26 { + reg = <0x26>;

- amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; + xbar_sfc4_in_ep: endpoint { + remote-endpoint = <&sfc4_cif_in_ep>; }; + };

- port@1 { - reg = <1>; + port@27 { + reg = <0x27>;

- amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; + xbar_sfc4_out_ep: endpoint { + remote-endpoint = <&sfc4_cif_out_ep>; }; + };

- amx2_in3_port: port@2 { - reg = <2>; + xbar_mvc1_in_port: port@28 { + reg = <0x28>;

- amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; + xbar_mvc1_in_ep: endpoint { + remote-endpoint = <&mvc1_cif_in_ep>; }; + };

- amx2_in4_port: port@3 { - reg = <3>; + port@29 { + reg = <0x29>;

- amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; + xbar_mvc1_out_ep: endpoint { + remote-endpoint = <&mvc1_cif_out_ep>; }; + };

- amx2_out_port: port@4 { - reg = <4>; + xbar_mvc2_in_port: port@2a { + reg = <0x2a>;

- amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; + xbar_mvc2_in_ep: endpoint { + remote-endpoint = <&mvc2_cif_in_ep>; }; }; - };

- amx@2903200 { - status = "okay"; + port@2b { + reg = <0x2b>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_mvc2_out_ep: endpoint { + remote-endpoint = <&mvc2_cif_out_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1_ep: endpoint { + remote-endpoint = <&amx1_in1_ep>; + }; + };

- amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2_ep: endpoint { + remote-endpoint = <&amx1_in2_ep>; }; + };

- port@1 { - reg = <1>; + xbar_amx1_in3_port: port@2e { + reg = <0x2e>;

- amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; + xbar_amx1_in3_ep: endpoint { + remote-endpoint = <&amx1_in3_ep>; }; + };

- port@2 { - reg = <2>; + xbar_amx1_in4_port: port@2f { + reg = <0x2f>;

- amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; + xbar_amx1_in4_ep: endpoint { + remote-endpoint = <&amx1_in4_ep>; }; + };

- port@3 { - reg = <3>; + port@30 { + reg = <0x30>;

- amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; + xbar_amx1_out_ep: endpoint { + remote-endpoint = <&amx1_out_ep>; }; + };

- amx3_out_port: port@4 { - reg = <4>; + xbar_amx2_in1_port: port@31 { + reg = <0x31>;

- amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; + xbar_amx2_in1_ep: endpoint { + remote-endpoint = <&amx2_in1_ep>; }; }; - };

- amx@2903300 { - status = "okay"; + xbar_amx2_in2_port: port@32 { + reg = <0x32>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx2_in2_ep: endpoint { + remote-endpoint = <&amx2_in2_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx2_in3_port: port@33 { + reg = <0x33>;

- amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; + xbar_amx2_in3_ep: endpoint { + remote-endpoint = <&amx2_in3_ep>; }; + };

- port@1 { - reg = <1>; + xbar_amx2_in4_port: port@34 { + reg = <0x34>;

- amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; + xbar_amx2_in4_ep: endpoint { + remote-endpoint = <&amx2_in4_ep>; }; + };

- port@2 { - reg = <2>; + port@35 { + reg = <0x35>;

- amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; + xbar_amx2_out_ep: endpoint { + remote-endpoint = <&amx2_out_ep>; }; + };

- port@3 { - reg = <3>; + xbar_amx3_in1_port: port@36 { + reg = <0x36>;

- amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; + xbar_amx3_in1_ep: endpoint { + remote-endpoint = <&amx3_in1_ep>; }; + };

- amx4_out_port: port@4 { - reg = <4>; + xbar_amx3_in2_port: port@37 { + reg = <0x37>;

- amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; + xbar_amx3_in2_ep: endpoint { + remote-endpoint = <&amx3_in2_ep>; }; }; - };

- adx@2903800 { - status = "okay"; + xbar_amx3_in3_port: port@38 { + reg = <0x38>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx3_in3_ep: endpoint { + remote-endpoint = <&amx3_in3_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_amx3_in4_port: port@39 { + reg = <0x39>;

- adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; + xbar_amx3_in4_ep: endpoint { + remote-endpoint = <&amx3_in4_ep>; }; + };

- adx1_out1_port: port@1 { - reg = <1>; + port@3a { + reg = <0x3a>;

- adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; + xbar_amx3_out_ep: endpoint { + remote-endpoint = <&amx3_out_ep>; }; + };

- adx1_out2_port: port@2 { - reg = <2>; + xbar_amx4_in1_port: port@3b { + reg = <0x3b>;

- adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; + xbar_amx4_in1_ep: endpoint { + remote-endpoint = <&amx4_in1_ep>; }; + };

- adx1_out3_port: port@3 { - reg = <3>; + xbar_amx4_in2_port: port@3c { + reg = <0x3c>;

- adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; + xbar_amx4_in2_ep: endpoint { + remote-endpoint = <&amx4_in2_ep>; }; + };

- adx1_out4_port: port@4 { - reg = <4>; + xbar_amx4_in3_port: port@3d { + reg = <0x3d>;

- adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; + xbar_amx4_in3_ep: endpoint { + remote-endpoint = <&amx4_in3_ep>; }; }; - };

- adx@2903900 { - status = "okay"; + xbar_amx4_in4_port: port@3e { + reg = <0x3e>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_amx4_in4_ep: endpoint { + remote-endpoint = <&amx4_in4_ep>; + }; + };

- port@0 { - reg = <0>; + port@3f { + reg = <0x3f>;

- adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; + xbar_amx4_out_ep: endpoint { + remote-endpoint = <&amx4_out_ep>; }; + };

- adx2_out1_port: port@1 { - reg = <1>; + xbar_adx1_in_port: port@40 { + reg = <0x40>;

- adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; + xbar_adx1_in_ep: endpoint { + remote-endpoint = <&adx1_in_ep>; }; + };

- adx2_out2_port: port@2 { - reg = <2>; + port@41 { + reg = <0x41>;

- adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; + xbar_adx1_out1_ep: endpoint { + remote-endpoint = <&adx1_out1_ep>; }; + };

- adx2_out3_port: port@3 { - reg = <3>; + port@42 { + reg = <0x42>;

- adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; + xbar_adx1_out2_ep: endpoint { + remote-endpoint = <&adx1_out2_ep>; }; + };

- adx2_out4_port: port@4 { - reg = <4>; + port@43 { + reg = <0x43>;

- adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; + xbar_adx1_out3_ep: endpoint { + remote-endpoint = <&adx1_out3_ep>; }; }; - };

- adx@2903a00 { - status = "okay"; + port@44 { + reg = <0x44>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx1_out4_ep: endpoint { + remote-endpoint = <&adx1_out4_ep>; + }; + };

- port@0 { - reg = <0>; + xbar_adx2_in_port: port@45 { + reg = <0x45>;

- adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; + xbar_adx2_in_ep: endpoint { + remote-endpoint = <&adx2_in_ep>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1_ep: endpoint { + remote-endpoint = <&adx2_out1_ep>; }; + };

- adx3_out1_port: port@1 { - reg = <1>; + port@47 { + reg = <0x47>;

- adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; + xbar_adx2_out2_ep: endpoint { + remote-endpoint = <&adx2_out2_ep>; }; + };

- adx3_out2_port: port@2 { - reg = <2>; + port@48 { + reg = <0x48>;

- adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; + xbar_adx2_out3_ep: endpoint { + remote-endpoint = <&adx2_out3_ep>; }; + };

- adx3_out3_port: port@3 { - reg = <3>; + port@49 { + reg = <0x49>;

- adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; + xbar_adx2_out4_ep: endpoint { + remote-endpoint = <&adx2_out4_ep>; }; + };

- adx3_out4_port: port@4 { - reg = <4>; + xbar_adx3_in_port: port@4a { + reg = <0x4a>;

- adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; + xbar_adx3_in_ep: endpoint { + remote-endpoint = <&adx3_in_ep>; }; }; - };

- adx@2903b00 { - status = "okay"; + port@4b { + reg = <0x4b>;

- ports { - #address-cells = <1>; - #size-cells = <0>; + xbar_adx3_out1_ep: endpoint { + remote-endpoint = <&adx3_out1_ep>; + }; + };

- port@0 { - reg = <0>; + port@4c { + reg = <0x4c>;

- adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; + xbar_adx3_out2_ep: endpoint { + remote-endpoint = <&adx3_out2_ep>; }; + };

- adx4_out1_port: port@1 { - reg = <1>; + port@4d { + reg = <0x4d>;

- adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; + xbar_adx3_out3_ep: endpoint { + remote-endpoint = <&adx3_out3_ep>; }; + };

- adx4_out2_port: port@2 { - reg = <2>; + port@4e { + reg = <0x4e>;