On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:

From: Chris Wilson chris.p.wilson@intel.com

Ensure that the TLB of the OA unit is also invalidated on gen12 HW, as just invalidating the TLB of an engine is not enough.

Cc: stable@vger.kernel.org Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Signed-off-by: Chris Wilson chris.p.wilson@intel.com Cc: Fei Yang fei.yang@intel.com Cc: Andi Shyti andi.shyti@linux.intel.com Acked-by: Thomas Hellström thomas.hellstrom@linux.intel.com Signed-off-by: Mauro Carvalho Chehab mchehab@kernel.org

Acked-by: Tvrtko Ursulin tvrtko.ursulin@intel.com

Regards,

Tvrtko

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/

drivers/gpu/drm/i915/gt/intel_gt.c | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index c4d43da84d8e..1d84418e8676 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -11,6 +11,7 @@ #include "pxp/intel_pxp.h" #include "i915_drv.h" +#include "i915_perf_oa_regs.h" #include "intel_context.h" #include "intel_engine_pm.h" #include "intel_engine_regs.h" @@ -969,6 +970,15 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) awake |= engine->mask; }

• /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */
• if (awake &&

•    (IS_TIGERLAKE(i915) ||
  

•     IS_DG1(i915) ||
  

•     IS_ROCKETLAKE(i915) ||
  

•     IS_ALDERLAKE_S(i915) ||
  

•     IS_ALDERLAKE_P(i915)))
  

• intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
  

• spin_unlock_irq(&uncore->lock);

for_each_engine_masked(engine, gt, awake, tmp) {