This is v2 of https://patchwork.freedesktop.org/series/88015/
also making sure that LTTPRs are detected and initialized only if the DPCD and LTTPR revisions are > 1.4 as required by Display Port specification.
Cc: Ville Syrjälä ville.syrjala@linux.intel.com Cc: stable@vger.kernel.org # v5.11
Imre Deak (3): drm/i915/ilk-glk: Fix link training on links with LTTPRs drm/i915: Disable LTTPR support when the DPCD rev < 1.4 drm/i915: Disable LTTPR support when the LTTPR rev < 1.4
drivers/gpu/drm/i915/display/intel_dp.c | 4 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 ++ .../drm/i915/display/intel_dp_link_training.c | 66 ++++++++++++++----- .../drm/i915/display/intel_dp_link_training.h | 2 +- 4 files changed, 58 insertions(+), 21 deletions(-)
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000-0xF0007 range (3.6.5.1).
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate santiago.zarate@suse.com Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
+ /* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret;
+ /* + * Max timeout values: + * SKL-GLK: 1.6ms + * CNL: 3.2ms + * ICL+: 4ms + */ ret = DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | DP_AUX_CH_CTL_INTERRUPT | diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (intel_dp_is_edp(intel_dp)) + return false; + + /* + * Detecting LTTPRs must be avoided on platforms with an AUX timeout + * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). + */ + if (INTEL_GEN(i915) < 10) + return false; + if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { memset(intel_dp->lttpr_common_caps, 0, @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
- if (intel_dp_is_edp(intel_dp)) - return 0; - ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0;
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000-0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate santiago.zarate@suse.com Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
- /* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else
@@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret;
- /*
* Max timeout values:* SKL-GLK: 1.6ms* CNL: 3.2ms* ICL+: 4ms*/diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) {
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp))
return false;- /*
* Detecting LTTPRs must be avoided on platforms with an AUX timeout* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).*/- if (INTEL_GEN(i915) < 10)
return false;- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { memset(intel_dp->lttpr_common_caps, 0,
@@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
- if (intel_dp_is_edp(intel_dp))
return 0;- ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0;
-- 2.25.1
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000-0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate santiago.zarate@suse.com Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
- /* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else
@@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret;
- /*
* Max timeout values:* SKL-GLK: 1.6ms* CNL: 3.2ms* ICL+: 4ms*/diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) {
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp))
return false;- /*
* Detecting LTTPRs must be avoided on platforms with an AUX timeout* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).*/- if (INTEL_GEN(i915) < 10)
return false;- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { memset(intel_dp->lttpr_common_caps, 0,
@@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
- if (intel_dp_is_edp(intel_dp))
return 0;- ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0;
-- 2.25.1
-- Ville Syrjälä Intel
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000-0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate santiago.zarate@suse.com Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
- /* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else
@@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret;
- /*
* Max timeout values:* SKL-GLK: 1.6ms* CNL: 3.2ms* ICL+: 4ms*/diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) {
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp))
return false;- /*
* Detecting LTTPRs must be avoided on platforms with an AUX timeout* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).*/- if (INTEL_GEN(i915) < 10)
return false;- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { memset(intel_dp->lttpr_common_caps, 0,
@@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
- if (intel_dp_is_edp(intel_dp))
return 0;- ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0;
-- 2.25.1
-- Ville Syrjälä Intel
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000- 0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
What about Lyude's suggestion ( https://patchwork.freedesktop.org/patch/420369/#comment_756572) to drop the retries in intel_dp_aux_xfer() /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
And use only the retries in drm_dpcd_access?
Thanks Khaled
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate < santiago.zarate@suse.com> Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
- /* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else
@@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port-
base.port);
u32 ret;
- /*
* Max timeout values:* SKL-GLK: 1.6ms* CNL: 3.2ms* ICL+: 4ms*/diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) {
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp))
return false;- /*
* Detecting LTTPRs must be avoided on platforms withan AUX timeout
* period < 3.2ms. (see DP Standard v2.0, 2.11.2,3.6.6.1).
*/- if (INTEL_GEN(i915) < 10)
return false;- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp-
lttpr_common_caps) < 0) {
memset(intel_dp->lttpr_common_caps, 0,@@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
- if (intel_dp_is_edp(intel_dp))
return 0;- ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0;
-- 2.25.1
-- Ville Syrjälä Intel
On Fri, Mar 19, 2021 at 12:04:54AM +0200, Almahallawy, Khaled wrote:
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000- 0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
What about Lyude's suggestion ( https://patchwork.freedesktop.org/patch/420369/#comment_756572) to drop the retries in intel_dp_aux_xfer() /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
And use only the retries in drm_dpcd_access?
I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
Thanks Khaled
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate < santiago.zarate@suse.com> Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
+/* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port-
base.port);
u32 ret;
+/*
- Max timeout values:
- SKL-GLK: 1.6ms
- CNL: 3.2ms
- ICL+: 4ms
- */
ret = DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | DP_AUX_CH_CTL_INTERRUPT | diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) { +struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+if (intel_dp_is_edp(intel_dp)) +return false;
+/*
- Detecting LTTPRs must be avoided on platforms with
an AUX timeout
- period < 3.2ms. (see DP Standard v2.0, 2.11.2,
3.6.6.1).
- */
+if (INTEL_GEN(i915) < 10) +return false;
if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp-
lttpr_common_caps) < 0) {
memset(intel_dp->lttpr_common_caps, 0, @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
-if (intel_dp_is_edp(intel_dp)) -return 0;
ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0; -- 2.25.1
-- Ville Syrjälä Intel
On Fri, 2021-03-19 at 01:17 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 12:04:54AM +0200, Almahallawy, Khaled wrote:
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000- 0xF0007 range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
What about Lyude's suggestion ( https://patchwork.freedesktop.org/patch/420369/#comment_756572) to drop the retries in intel_dp_aux_xfer() /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
And use only the retries in drm_dpcd_access?
I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
Thanks Khaled
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms.
Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems.
While at it add a code comment about the platform specific maximum timeout values.
v2: Add a comment about the g4x maximum timeout as well. (Ville)
Reported-by: Takashi Iwai tiwai@suse.de Reported-and-tested-by: Santiago Zarate < santiago.zarate@suse.com> Reported-and-tested-by: Bodo Graumann mail@bodograumann.de References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Takashi Iwai tiwai@suse.de Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eaebf123310a..10fe17b7280d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, else precharge = 5;
+/* Max timeout value on G4x-BDW: 1.6ms */ if (IS_BROADWELL(dev_priv)) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, enum phy phy = intel_port_to_phy(i915, dig_port- > base.port); u32 ret;
+/*
- Max timeout values:
- SKL-GLK: 1.6ms
- CNL: 3.2ms
- ICL+: 4ms
- */
ret = DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE | DP_AUX_CH_CTL_INTERRUPT | diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 19ba7c7cbaab..c0e25c75c105 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -82,6 +82,18 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) { +struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+if (intel_dp_is_edp(intel_dp)) +return false;
+/*
- Detecting LTTPRs must be avoided on platforms with
an AUX timeout
- period < 3.2ms. (see DP Standard v2.0, 2.11.2,
3.6.6.1).
- */
+if (INTEL_GEN(i915) < 10) +return false;
if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp- > lttpr_common_caps) < 0) { memset(intel_dp->lttpr_common_caps, 0, @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) bool ret; int i;
-if (intel_dp_is_edp(intel_dp)) -return 0;
ret = intel_dp_read_lttpr_common_caps(intel_dp); if (!ret) return 0; -- 2.25.1
-- Ville Syrjälä Intel
On Fri, Mar 19, 2021 at 01:25:08PM -0400, Lyude Paul wrote:
On Fri, 2021-03-19 at 01:17 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 12:04:54AM +0200, Almahallawy, Khaled wrote:
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote: > The spec requires to use at least 3.2ms for the AUX timeout > period if > there are LT-tunable PHY Repeaters on the link (2.11.2). An > upcoming > spec update makes this more specific, by requiring a 3.2ms > minimum > timeout period for the LTTPR detection reading the 0xF0000- > 0xF0007 > range (3.6.5.1).
I'm pondering if we could reduce the timeout after having determined wherther LTTPRs are present or not? But maybe that wouldn't really speed up anything since we can't reduce the timeout until after detecting *something*. And once there is something there we shouldn't really get any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
What about Lyude's suggestion ( https://patchwork.freedesktop.org/patch/420369/#comment_756572) to drop the retries in intel_dp_aux_xfer() /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
And use only the retries in drm_dpcd_access?
I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
Thanks Khaled
Anyways, this seems about the only thing we can do given the limited hw capabilities. Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
> Accordingly disable LTTPR detection until GLK, where the > maximum timeout > we can set is only 1.6ms. > > Link training in the non-transparent mode is known to fail at > least on > some SKL systems with a WD19 dock on the link, which exposes an > LTTPR > (see the References below). While this could have different > reasons > besides the too short AUX timeout used, not detecting LTTPRs > (and so not > using the non-transparent LT mode) fixes link training on these > systems. > > While at it add a code comment about the platform specific > maximum > timeout values. > > v2: Add a comment about the g4x maximum timeout as well. > (Ville) > > Reported-by: Takashi Iwai tiwai@suse.de > Reported-and-tested-by: Santiago Zarate < > santiago.zarate@suse.com> > Reported-and-tested-by: Bodo Graumann mail@bodograumann.de > References: > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent > mode link training") > Cc: stable@vger.kernel.org # v5.11 > Cc: Takashi Iwai tiwai@suse.de > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > Signed-off-by: Imre Deak imre.deak@intel.com > --- > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ > .../gpu/drm/i915/display/intel_dp_link_training.c | 15 > ++++++++++++--- > 2 files changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > index eaebf123310a..10fe17b7280d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct > intel_dp *intel_dp, > else > precharge = 5; > > +/* Max timeout value on G4x-BDW: 1.6ms */ > if (IS_BROADWELL(dev_priv)) > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > else > @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct > intel_dp *intel_dp, > enum phy phy = intel_port_to_phy(i915, dig_port- > > base.port); > u32 ret; > > +/* > + * Max timeout values: > + * SKL-GLK: 1.6ms > + * CNL: 3.2ms > + * ICL+: 4ms > + */ > ret = DP_AUX_CH_CTL_SEND_BUSY | > DP_AUX_CH_CTL_DONE | > DP_AUX_CH_CTL_INTERRUPT | > diff --git > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 19ba7c7cbaab..c0e25c75c105 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -82,6 +82,18 @@ static void > intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, > > static bool intel_dp_read_lttpr_common_caps(struct intel_dp > *intel_dp) > { > +struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + > +if (intel_dp_is_edp(intel_dp)) > +return false; > + > +/* > + * Detecting LTTPRs must be avoided on platforms with > an AUX timeout > + * period < 3.2ms. (see DP Standard v2.0, 2.11.2, > 3.6.6.1). > + */ > +if (INTEL_GEN(i915) < 10) > +return false; > + > if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, > intel_dp- > > lttpr_common_caps) < 0) { > memset(intel_dp->lttpr_common_caps, 0, > @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp > *intel_dp) > bool ret; > int i; > > -if (intel_dp_is_edp(intel_dp)) > -return 0; > - > ret = intel_dp_read_lttpr_common_caps(intel_dp); > if (!ret) > return 0; > -- > 2.25.1
-- Ville Syrjälä Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
On Fri, 2021-03-19 at 19:29 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 01:25:08PM -0400, Lyude Paul wrote:
On Fri, 2021-03-19 at 01:17 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 12:04:54AM +0200, Almahallawy, Khaled wrote:
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote: > On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote: > > The spec requires to use at least 3.2ms for the AUX timeout > > period if > > there are LT-tunable PHY Repeaters on the link (2.11.2). An > > upcoming > > spec update makes this more specific, by requiring a 3.2ms > > minimum > > timeout period for the LTTPR detection reading the 0xF0000- > > 0xF0007 > > range (3.6.5.1). > > I'm pondering if we could reduce the timeout after having > determined > wherther LTTPRs are present or not? But maybe that wouldn't > really speed > up anything since we can't reduce the timeout until after > detecting > *something*. And once there is something there we shouldn't > really get > any more timeouts I guess. So probably a totally stupid idea.
Right, if something is connected it would take anyway as much time as it takes for the sink to reply whether or not we decreased the timeout.
However if nothing is connected, we have the excessive timeout Khaled already noticed (160 * 4ms = 6.4 sec on ICL+). I think to improve that we could scale the total number of retries by making it total_timeout/platform_specific_timeout (letting total_timeout=2sec for instance) or just changing the drm retry logic to be time based instead of the number of retries we use atm.
Doh, reducing simply the HW timeouts would be enough to fix this.
What about Lyude's suggestion ( https://patchwork.freedesktop.org/patch/420369/#comment_756572) to drop the retries in intel_dp_aux_xfer() /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
And use only the retries in drm_dpcd_access?
I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
You mean the
/* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
bit? I thought that wasn't related to platform specific retries at all, since the code in that loop seems to only reference parts of the DP spec, and that the
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Loop was the portion that was platform specific, since it prompts the driver to retry the transaction with different aux clock divider rates depending on the platform in use. Feel free to correct me if I'm wrong though.
Also - with the timeouts we're seeing, does the LTTPR return NAKs at all? That's still another thing I had suggested alternate workarounds for so that we could terminate transactions immediately on NAKs, so I wonder if that could save time here as well.
Thanks Khaled
> Anyways, this seems about the only thing we can do given the > limited > hw capabilities. > Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com > > > Accordingly disable LTTPR detection until GLK, where the > > maximum timeout > > we can set is only 1.6ms. > > > > Link training in the non-transparent mode is known to fail at > > least on > > some SKL systems with a WD19 dock on the link, which exposes an > > LTTPR > > (see the References below). While this could have different > > reasons > > besides the too short AUX timeout used, not detecting LTTPRs > > (and so not > > using the non-transparent LT mode) fixes link training on these > > systems. > > > > While at it add a code comment about the platform specific > > maximum > > timeout values. > > > > v2: Add a comment about the g4x maximum timeout as well. > > (Ville) > > > > Reported-by: Takashi Iwai tiwai@suse.de > > Reported-and-tested-by: Santiago Zarate < > > santiago.zarate@suse.com> > > Reported-and-tested-by: Bodo Graumann mail@bodograumann.de > > References: > > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent > > mode link training") > > Cc: stable@vger.kernel.org # v5.11 > > Cc: Takashi Iwai tiwai@suse.de > > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > > Signed-off-by: Imre Deak imre.deak@intel.com > > --- > > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ > > .../gpu/drm/i915/display/intel_dp_link_training.c | 15 > > ++++++++++++--- > > 2 files changed, 19 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > index eaebf123310a..10fe17b7280d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct > > intel_dp *intel_dp, > > else > > precharge = 5; > > > > +/* Max timeout value on G4x-BDW: 1.6ms */ > > if (IS_BROADWELL(dev_priv)) > > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > > else > > @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct > > intel_dp *intel_dp, > > enum phy phy = intel_port_to_phy(i915, dig_port- > > > base.port); > > u32 ret; > > > > +/* > > + * Max timeout values: > > + * SKL-GLK: 1.6ms > > + * CNL: 3.2ms > > + * ICL+: 4ms > > + */ > > ret = DP_AUX_CH_CTL_SEND_BUSY | > > DP_AUX_CH_CTL_DONE | > > DP_AUX_CH_CTL_INTERRUPT | > > diff --git > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > index 19ba7c7cbaab..c0e25c75c105 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > @@ -82,6 +82,18 @@ static void > > intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, > > > > static bool intel_dp_read_lttpr_common_caps(struct intel_dp > > *intel_dp) > > { > > +struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > + > > +if (intel_dp_is_edp(intel_dp)) > > +return false; > > + > > +/* > > + * Detecting LTTPRs must be avoided on platforms with > > an AUX timeout > > + * period < 3.2ms. (see DP Standard v2.0, 2.11.2, > > 3.6.6.1). > > + */ > > +if (INTEL_GEN(i915) < 10) > > +return false; > > + > > if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, > > intel_dp- > > > lttpr_common_caps) < 0) { > > memset(intel_dp->lttpr_common_caps, 0, > > @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp > > *intel_dp) > > bool ret; > > int i; > > > > -if (intel_dp_is_edp(intel_dp)) > > -return 0; > > - > > ret = intel_dp_read_lttpr_common_caps(intel_dp); > > if (!ret) > > return 0; > > -- > > 2.25.1 > > -- > Ville Syrjälä > Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
On Fri, Mar 19, 2021 at 04:44:26PM -0400, Lyude Paul wrote:
[...] I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
You mean the
/* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {bit? I thought that wasn't related to platform specific retries at all, since the code in that loop seems to only reference parts of the DP spec, and that the
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Loop was the portion that was platform specific, since it prompts the driver to retry the transaction with different aux clock divider rates depending on the platform in use. Feel free to correct me if I'm wrong though.
Nope. I meant every HW transaction will have a platform specific timeout. For instance it's 1.6ms on SKL, but 4ms on ICL. So now since the overall retry count is 32 * 5 = 160, on SKL we'll retry for ~2.6 seconds, on ICL we'll retry for ~6.4 seconds (disregarding now the extra 400usec delay inserted by drm_dp_dpcd_access(), which adds a fixed ~1.3ms delay).
This is what I think should be normalized, so that we have the same amount of overall maximum timeout period on all platforms.
Also - with the timeouts we're seeing, does the LTTPR return NAKs at all? That's still another thing I had suggested alternate workarounds for so that we could terminate transactions immediately on NAKs, so I wonder if that could save time here as well.
There's not much LTTPR specific in that wrt. what sinks would do normally (no NAKs for read, only for writes) except LTTPRs may rewrite NAKs to ACKs to account for buggy monitors returning NAKs when reading the 0xf0000 -> range. But I'd suggest not dealing with this aspect now, just sanitize the above retry thing, as you suggested, remove the i915 retry loop and make the drm retry loop configurable.
(In any case I also had the idea to stop transactions early when HPD gets deasserted, but not sure if that's completely robust.)
Thanks Khaled
> > Anyways, this seems about the only thing we can do given the > > limited > > hw capabilities. > > Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com > > > > > Accordingly disable LTTPR detection until GLK, where the > > > maximum timeout > > > we can set is only 1.6ms. > > > > > > Link training in the non-transparent mode is known to fail at > > > least on > > > some SKL systems with a WD19 dock on the link, which exposes an > > > LTTPR > > > (see the References below). While this could have different > > > reasons > > > besides the too short AUX timeout used, not detecting LTTPRs > > > (and so not > > > using the non-transparent LT mode) fixes link training on these > > > systems. > > > > > > While at it add a code comment about the platform specific > > > maximum > > > timeout values. > > > > > > v2: Add a comment about the g4x maximum timeout as well. > > > (Ville) > > > > > > Reported-by: Takashi Iwai tiwai@suse.de > > > Reported-and-tested-by: Santiago Zarate < > > > santiago.zarate@suse.com> > > > Reported-and-tested-by: Bodo Graumann mail@bodograumann.de > > > References: > > > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent > > > mode link training") > > > Cc: stable@vger.kernel.org # v5.11 > > > Cc: Takashi Iwai tiwai@suse.de > > > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > > > Signed-off-by: Imre Deak imre.deak@intel.com > > > --- > > > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ > > > .../gpu/drm/i915/display/intel_dp_link_training.c | 15 > > > ++++++++++++--- > > > 2 files changed, 19 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > index eaebf123310a..10fe17b7280d 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct > > > intel_dp *intel_dp, > > > else > > > precharge = 5; > > > > > > +/* Max timeout value on G4x-BDW: 1.6ms */ > > > if (IS_BROADWELL(dev_priv)) > > > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > > > else > > > @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct > > > intel_dp *intel_dp, > > > enum phy phy = intel_port_to_phy(i915, dig_port- > > > > base.port); > > > u32 ret; > > > > > > +/* > > > + * Max timeout values: > > > + * SKL-GLK: 1.6ms > > > + * CNL: 3.2ms > > > + * ICL+: 4ms > > > + */ > > > ret = DP_AUX_CH_CTL_SEND_BUSY | > > > DP_AUX_CH_CTL_DONE | > > > DP_AUX_CH_CTL_INTERRUPT | > > > diff --git > > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > index 19ba7c7cbaab..c0e25c75c105 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > @@ -82,6 +82,18 @@ static void > > > intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, > > > > > > static bool intel_dp_read_lttpr_common_caps(struct intel_dp > > > *intel_dp) > > > { > > > +struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > + > > > +if (intel_dp_is_edp(intel_dp)) > > > +return false; > > > + > > > +/* > > > + * Detecting LTTPRs must be avoided on platforms with > > > an AUX timeout > > > + * period < 3.2ms. (see DP Standard v2.0, 2.11.2, > > > 3.6.6.1). > > > + */ > > > +if (INTEL_GEN(i915) < 10) > > > +return false; > > > + > > > if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, > > > intel_dp- > > > > lttpr_common_caps) < 0) { > > > memset(intel_dp->lttpr_common_caps, 0, > > > @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp > > > *intel_dp) > > > bool ret; > > > int i; > > > > > > -if (intel_dp_is_edp(intel_dp)) > > > -return 0; > > > - > > > ret = intel_dp_read_lttpr_common_caps(intel_dp); > > > if (!ret) > > > return 0; > > > -- > > > 2.25.1 > > > > -- > > Ville Syrjälä > > Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
On Fri, Mar 19, 2021 at 11:07:21PM +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 04:44:26PM -0400, Lyude Paul wrote:
[...] I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
You mean the
/* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {bit? I thought that wasn't related to platform specific retries at all, since the code in that loop seems to only reference parts of the DP spec, and that the
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Loop was the portion that was platform specific, since it prompts the driver to retry the transaction with different aux clock divider rates depending on the platform in use. Feel free to correct me if I'm wrong though.
Nope. I meant every HW transaction will have a platform specific timeout. For instance it's 1.6ms on SKL, but 4ms on ICL. So now since the overall retry count is 32 * 5 = 160, on SKL we'll retry for ~2.6 seconds, on ICL we'll retry for ~6.4 seconds (disregarding now the extra 400usec delay inserted by drm_dp_dpcd_access(), which adds a fixed ~1.3ms delay).
Err, looks like I missed some coffee. Max total timeouts atm, which we would need to make the same on all platforms:
g4x-glk: 5 * 32 * 1.6ms + 32 * 400us = 268.8ms cnl : 5 * 32 * 3.2ms + 32 * 400us = 524.8ms icl+ : 5 * 32 * 4ms + 32 * 400us = 652.8ms
This is what I think should be normalized, so that we have the same amount of overall maximum timeout period on all platforms.
Also - with the timeouts we're seeing, does the LTTPR return NAKs at all? That's still another thing I had suggested alternate workarounds for so that we could terminate transactions immediately on NAKs, so I wonder if that could save time here as well.
There's not much LTTPR specific in that wrt. what sinks would do normally (no NAKs for read, only for writes) except LTTPRs may rewrite NAKs to ACKs to account for buggy monitors returning NAKs when reading the 0xf0000 -> range. But I'd suggest not dealing with this aspect now, just sanitize the above retry thing, as you suggested, remove the i915 retry loop and make the drm retry loop configurable.
(In any case I also had the idea to stop transactions early when HPD gets deasserted, but not sure if that's completely robust.)
Thanks Khaled
> > > > Anyways, this seems about the only thing we can do given the > > > limited > > > hw capabilities. > > > Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com > > > > > > > Accordingly disable LTTPR detection until GLK, where the > > > > maximum timeout > > > > we can set is only 1.6ms. > > > > > > > > Link training in the non-transparent mode is known to fail at > > > > least on > > > > some SKL systems with a WD19 dock on the link, which exposes an > > > > LTTPR > > > > (see the References below). While this could have different > > > > reasons > > > > besides the too short AUX timeout used, not detecting LTTPRs > > > > (and so not > > > > using the non-transparent LT mode) fixes link training on these > > > > systems. > > > > > > > > While at it add a code comment about the platform specific > > > > maximum > > > > timeout values. > > > > > > > > v2: Add a comment about the g4x maximum timeout as well. > > > > (Ville) > > > > > > > > Reported-by: Takashi Iwai tiwai@suse.de > > > > Reported-and-tested-by: Santiago Zarate < > > > > santiago.zarate@suse.com> > > > > Reported-and-tested-by: Bodo Graumann mail@bodograumann.de > > > > References: > > > > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > > > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent > > > > mode link training") > > > > Cc: stable@vger.kernel.org # v5.11 > > > > Cc: Takashi Iwai tiwai@suse.de > > > > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > > > > Signed-off-by: Imre Deak imre.deak@intel.com > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ > > > > .../gpu/drm/i915/display/intel_dp_link_training.c | 15 > > > > ++++++++++++--- > > > > 2 files changed, 19 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > index eaebf123310a..10fe17b7280d 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > @@ -133,6 +133,7 @@ static u32 g4x_get_aux_send_ctl(struct > > > > intel_dp *intel_dp, > > > > else > > > > precharge = 5; > > > > > > > > +/* Max timeout value on G4x-BDW: 1.6ms */ > > > > if (IS_BROADWELL(dev_priv)) > > > > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > > > > else > > > > @@ -159,6 +160,12 @@ static u32 skl_get_aux_send_ctl(struct > > > > intel_dp *intel_dp, > > > > enum phy phy = intel_port_to_phy(i915, dig_port- > > > > > base.port); > > > > u32 ret; > > > > > > > > +/* > > > > + * Max timeout values: > > > > + * SKL-GLK: 1.6ms > > > > + * CNL: 3.2ms > > > > + * ICL+: 4ms > > > > + */ > > > > ret = DP_AUX_CH_CTL_SEND_BUSY | > > > > DP_AUX_CH_CTL_DONE | > > > > DP_AUX_CH_CTL_INTERRUPT | > > > > diff --git > > > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > > index 19ba7c7cbaab..c0e25c75c105 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > > @@ -82,6 +82,18 @@ static void > > > > intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, > > > > > > > > static bool intel_dp_read_lttpr_common_caps(struct intel_dp > > > > *intel_dp) > > > > { > > > > +struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > + > > > > +if (intel_dp_is_edp(intel_dp)) > > > > +return false; > > > > + > > > > +/* > > > > + * Detecting LTTPRs must be avoided on platforms with > > > > an AUX timeout > > > > + * period < 3.2ms. (see DP Standard v2.0, 2.11.2, > > > > 3.6.6.1). > > > > + */ > > > > +if (INTEL_GEN(i915) < 10) > > > > +return false; > > > > + > > > > if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, > > > > intel_dp- > > > > > lttpr_common_caps) < 0) { > > > > memset(intel_dp->lttpr_common_caps, 0, > > > > @@ -127,9 +139,6 @@ int intel_dp_lttpr_init(struct intel_dp > > > > *intel_dp) > > > > bool ret; > > > > int i; > > > > > > > > -if (intel_dp_is_edp(intel_dp)) > > > > -return 0; > > > > - > > > > ret = intel_dp_read_lttpr_common_caps(intel_dp); > > > > if (!ret) > > > > return 0; > > > > -- > > > > 2.25.1 > > > > > > -- > > > Ville Syrjälä > > > Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
On Sat, 2021-03-20 at 09:15 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 11:07:21PM +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 04:44:26PM -0400, Lyude Paul wrote:
[...] I think it would work if we can make the retries configurable and set it to retries = total_timeout / platform_specific_timeout_per_retry
where total_timeout would be something reasonable like 1 sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
You mean the
/* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {bit? I thought that wasn't related to platform specific retries at all, since the code in that loop seems to only reference parts of the DP spec, and that the
while ((aux_clock_divider = intel_dp-
get_aux_clock_divider(intel_dp, clock++))) {
Loop was the portion that was platform specific, since it prompts the driver to retry the transaction with different aux clock divider rates depending on the platform in use. Feel free to correct me if I'm wrong though.
Nope. I meant every HW transaction will have a platform specific timeout. For instance it's 1.6ms on SKL, but 4ms on ICL. So now since the overall retry count is 32 * 5 = 160, on SKL we'll retry for ~2.6 seconds, on ICL we'll retry for ~6.4 seconds (disregarding now the extra 400usec delay inserted by drm_dp_dpcd_access(), which adds a fixed ~1.3ms delay).
Err, looks like I missed some coffee. Max total timeouts atm, which we would need to make the same on all platforms:
g4x-glk: 5 * 32 * 1.6ms + 32 * 400us = 268.8ms cnl : 5 * 32 * 3.2ms + 32 * 400us = 524.8ms icl+ : 5 * 32 * 4ms + 32 * 400us = 652.8ms
Apology if I'm missing something. but in drm_dpcd_access() I think it is 500us not 400us?!
#define AUX_RETRY_INTERVAL 500 /* us */
if (ret != 0 && ret != -ETIMEDOUT) { usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); }
Thanks Khaled
This is what I think should be normalized, so that we have the same amount of overall maximum timeout period on all platforms.
Also - with the timeouts we're seeing, does the LTTPR return NAKs at all? That's still another thing I had suggested alternate workarounds for so that we could terminate transactions immediately on NAKs, so I wonder if that could save time here as well.
There's not much LTTPR specific in that wrt. what sinks would do normally (no NAKs for read, only for writes) except LTTPRs may rewrite NAKs to ACKs to account for buggy monitors returning NAKs when reading the 0xf0000 -> range. But I'd suggest not dealing with this aspect now, just sanitize the above retry thing, as you suggested, remove the i915 retry loop and make the drm retry loop configurable.
(In any case I also had the idea to stop transactions early when HPD gets deasserted, but not sure if that's completely robust.)
> Thanks > Khaled > > > > > Anyways, this seems about the only thing we can do > > > > given the > > > > limited > > > > hw capabilities. > > > > Reviewed-by: Ville Syrjälä < > > > > ville.syrjala@linux.intel.com> > > > > > > > > > Accordingly disable LTTPR detection until GLK, > > > > > where the > > > > > maximum timeout > > > > > we can set is only 1.6ms. > > > > > > > > > > Link training in the non-transparent mode is > > > > > known to fail at > > > > > least on > > > > > some SKL systems with a WD19 dock on the link, > > > > > which exposes an > > > > > LTTPR > > > > > (see the References below). While this could have > > > > > different > > > > > reasons > > > > > besides the too short AUX timeout used, not > > > > > detecting LTTPRs > > > > > (and so not > > > > > using the non-transparent LT mode) fixes link > > > > > training on these > > > > > systems. > > > > > > > > > > While at it add a code comment about the platform > > > > > specific > > > > > maximum > > > > > timeout values. > > > > > > > > > > v2: Add a comment about the g4x maximum timeout > > > > > as well. > > > > > (Ville) > > > > > > > > > > Reported-by: Takashi Iwai tiwai@suse.de > > > > > Reported-and-tested-by: Santiago Zarate < > > > > > santiago.zarate@suse.com> > > > > > Reported-and-tested-by: Bodo Graumann < > > > > > mail@bodograumann.de> > > > > > References: > > > > > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > > > > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR > > > > > non-transparent > > > > > mode link training") > > > > > Cc: stable@vger.kernel.org # v5.11 > > > > > Cc: Takashi Iwai tiwai@suse.de > > > > > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > > > > > Signed-off-by: Imre Deak imre.deak@intel.com > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > | 7 +++++++ > > > > > .../gpu/drm/i915/display/intel_dp_link_training. > > > > > c | 15 > > > > > ++++++++++++--- > > > > > 2 files changed, 19 insertions(+), 3 deletions(- > > > > > ) > > > > > > > > > > diff --git > > > > > a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > index eaebf123310a..10fe17b7280d 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > @@ -133,6 +133,7 @@ static u32 > > > > > g4x_get_aux_send_ctl(struct > > > > > intel_dp *intel_dp, > > > > > else > > > > > precharge = 5; > > > > > > > > > > +/* Max timeout value on G4x-BDW: 1.6ms */ > > > > > if (IS_BROADWELL(dev_priv)) > > > > > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > > > > > else > > > > > @@ -159,6 +160,12 @@ static u32 > > > > > skl_get_aux_send_ctl(struct > > > > > intel_dp *intel_dp, > > > > > enum phy phy = intel_port_to_phy(i915, dig_port- > > > > > > base.port); > > > > > u32 ret; > > > > > > > > > > +/* > > > > > + * Max timeout values: > > > > > + * SKL-GLK: 1.6ms > > > > > + * CNL: 3.2ms > > > > > + * ICL+: 4ms > > > > > + */ > > > > > ret = DP_AUX_CH_CTL_SEND_BUSY | > > > > > DP_AUX_CH_CTL_DONE | > > > > > DP_AUX_CH_CTL_INTERRUPT | > > > > > diff --git > > > > > a/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > ning.c > > > > > b/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > ning.c > > > > > index 19ba7c7cbaab..c0e25c75c105 100644 > > > > > --- > > > > > a/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > ning.c > > > > > +++ > > > > > b/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > ning.c > > > > > @@ -82,6 +82,18 @@ static void > > > > > intel_dp_read_lttpr_phy_caps(struct intel_dp > > > > > *intel_dp, > > > > > > > > > > static bool > > > > > intel_dp_read_lttpr_common_caps(struct intel_dp > > > > > *intel_dp) > > > > > { > > > > > +struct drm_i915_private *i915 = > > > > > dp_to_i915(intel_dp); > > > > > + > > > > > +if (intel_dp_is_edp(intel_dp)) > > > > > +return false; > > > > > + > > > > > +/* > > > > > + * Detecting LTTPRs must be avoided on platforms > > > > > with > > > > > an AUX timeout > > > > > + * period < 3.2ms. (see DP Standard v2.0, > > > > > 2.11.2, > > > > > 3.6.6.1). > > > > > + */ > > > > > +if (INTEL_GEN(i915) < 10) > > > > > +return false; > > > > > + > > > > > if (drm_dp_read_lttpr_common_caps(&intel_dp- > > > > > >aux, > > > > > intel_dp- > > > > > > lttpr_common_caps) < 0) { > > > > > memset(intel_dp->lttpr_common_caps, 0, > > > > > @@ -127,9 +139,6 @@ int > > > > > intel_dp_lttpr_init(struct intel_dp > > > > > *intel_dp) > > > > > bool ret; > > > > > int i; > > > > > > > > > > -if (intel_dp_is_edp(intel_dp)) > > > > > -return 0; > > > > > - > > > > > ret = intel_dp_read_lttpr_common_caps(intel_dp); > > > > > if (!ret) > > > > > return 0; > > > > > -- > > > > > 2.25.1 > > > > > > > > -- > > > > Ville Syrjälä > > > > Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
On Sat, Mar 20, 2021 at 09:40:52AM +0200, Almahallawy, Khaled wrote:
On Sat, 2021-03-20 at 09:15 +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 11:07:21PM +0200, Imre Deak wrote:
On Fri, Mar 19, 2021 at 04:44:26PM -0400, Lyude Paul wrote:
> [...] > I think it would work if we can make the retries > configurable and set it > to > retries = total_timeout / > platform_specific_timeout_per_retry > > where total_timeout would be something reasonable like 1 > sec.
I actually think I'm more open to the idea of configurable retries after learning that apparently this is a thing that the i2c subsystem does - so there's more precedence for it in the rest of the kernel than I originally thought.
I'm still curious if we need these extra retries in here though - there seems to be one set of retries that is actually platform specific, and then just a random set of 5 retries that don't seem to have anything to do with platform specific behavior - so I think it'd still be worth giving a shot at getting rid of that
The platform specific part of the timeout is the one desctibed in the maximum timeout values comments.
You mean the
/* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) {
bit? I thought that wasn't related to platform specific retries at all, since the code in that loop seems to only reference parts of the DP spec, and that the
while ((aux_clock_divider = intel_dp-
get_aux_clock_divider(intel_dp, clock++))) {
Loop was the portion that was platform specific, since it prompts the driver to retry the transaction with different aux clock divider rates depending on the platform in use. Feel free to correct me if I'm wrong though.
Nope. I meant every HW transaction will have a platform specific timeout. For instance it's 1.6ms on SKL, but 4ms on ICL. So now since the overall retry count is 32 * 5 = 160, on SKL we'll retry for ~2.6 seconds, on ICL we'll retry for ~6.4 seconds (disregarding now the extra 400usec delay inserted by drm_dp_dpcd_access(), which adds a fixed ~1.3ms delay).
Err, looks like I missed some coffee. Max total timeouts atm, which we would need to make the same on all platforms:
g4x-glk: 5 * 32 * 1.6ms + 32 * 400us = 268.8ms cnl : 5 * 32 * 3.2ms + 32 * 400us = 524.8ms icl+ : 5 * 32 * 4ms + 32 * 400us = 652.8ms
Apology if I'm missing something. but in drm_dpcd_access() I think it is 500us not 400us?!
Ah, yes, or more like 600us so need to add 6.4ms to all of the above figures.
#define AUX_RETRY_INTERVAL 500 /* us */
if (ret != 0 && ret != -ETIMEDOUT) { usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); }
Thanks Khaled
This is what I think should be normalized, so that we have the same amount of overall maximum timeout period on all platforms.
Also - with the timeouts we're seeing, does the LTTPR return NAKs at all? That's still another thing I had suggested alternate workarounds for so that we could terminate transactions immediately on NAKs, so I wonder if that could save time here as well.
There's not much LTTPR specific in that wrt. what sinks would do normally (no NAKs for read, only for writes) except LTTPRs may rewrite NAKs to ACKs to account for buggy monitors returning NAKs when reading the 0xf0000 -> range. But I'd suggest not dealing with this aspect now, just sanitize the above retry thing, as you suggested, remove the i915 retry loop and make the drm retry loop configurable.
(In any case I also had the idea to stop transactions early when HPD gets deasserted, but not sure if that's completely robust.)
> > Thanks > > Khaled > > > > > > > Anyways, this seems about the only thing we can do > > > > > given the > > > > > limited > > > > > hw capabilities. > > > > > Reviewed-by: Ville Syrjälä < > > > > > ville.syrjala@linux.intel.com> > > > > > > > > > > > Accordingly disable LTTPR detection until GLK, > > > > > > where the > > > > > > maximum timeout > > > > > > we can set is only 1.6ms. > > > > > > > > > > > > Link training in the non-transparent mode is > > > > > > known to fail at > > > > > > least on > > > > > > some SKL systems with a WD19 dock on the link, > > > > > > which exposes an > > > > > > LTTPR > > > > > > (see the References below). While this could have > > > > > > different > > > > > > reasons > > > > > > besides the too short AUX timeout used, not > > > > > > detecting LTTPRs > > > > > > (and so not > > > > > > using the non-transparent LT mode) fixes link > > > > > > training on these > > > > > > systems. > > > > > > > > > > > > While at it add a code comment about the platform > > > > > > specific > > > > > > maximum > > > > > > timeout values. > > > > > > > > > > > > v2: Add a comment about the g4x maximum timeout > > > > > > as well. > > > > > > (Ville) > > > > > > > > > > > > Reported-by: Takashi Iwai tiwai@suse.de > > > > > > Reported-and-tested-by: Santiago Zarate < > > > > > > santiago.zarate@suse.com> > > > > > > Reported-and-tested-by: Bodo Graumann < > > > > > > mail@bodograumann.de> > > > > > > References: > > > > > > https://gitlab.freedesktop.org/drm/intel/-/issues/3166 > > > > > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR > > > > > > non-transparent > > > > > > mode link training") > > > > > > Cc: stable@vger.kernel.org # v5.11 > > > > > > Cc: Takashi Iwai tiwai@suse.de > > > > > > Cc: Ville Syrjälä ville.syrjala@linux.intel.com > > > > > > Signed-off-by: Imre Deak imre.deak@intel.com > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > > | 7 +++++++ > > > > > > .../gpu/drm/i915/display/intel_dp_link_training. > > > > > > c | 15 > > > > > > ++++++++++++--- > > > > > > 2 files changed, 19 insertions(+), 3 deletions(- > > > > > > ) > > > > > > > > > > > > diff --git > > > > > > a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > > index eaebf123310a..10fe17b7280d 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > > > > > > @@ -133,6 +133,7 @@ static u32 > > > > > > g4x_get_aux_send_ctl(struct > > > > > > intel_dp *intel_dp, > > > > > > else > > > > > > precharge = 5; > > > > > > > > > > > > +/* Max timeout value on G4x-BDW: 1.6ms */ > > > > > > if (IS_BROADWELL(dev_priv)) > > > > > > timeout = DP_AUX_CH_CTL_TIME_OUT_600us; > > > > > > else > > > > > > @@ -159,6 +160,12 @@ static u32 > > > > > > skl_get_aux_send_ctl(struct > > > > > > intel_dp *intel_dp, > > > > > > enum phy phy = intel_port_to_phy(i915, dig_port- > > > > > > > base.port); > > > > > > u32 ret; > > > > > > > > > > > > +/* > > > > > > + * Max timeout values: > > > > > > + * SKL-GLK: 1.6ms > > > > > > + * CNL: 3.2ms > > > > > > + * ICL+: 4ms > > > > > > + */ > > > > > > ret = DP_AUX_CH_CTL_SEND_BUSY | > > > > > > DP_AUX_CH_CTL_DONE | > > > > > > DP_AUX_CH_CTL_INTERRUPT | > > > > > > diff --git > > > > > > a/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > > ning.c > > > > > > b/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > > ning.c > > > > > > index 19ba7c7cbaab..c0e25c75c105 100644 > > > > > > --- > > > > > > a/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > > ning.c > > > > > > +++ > > > > > > b/drivers/gpu/drm/i915/display/intel_dp_link_trai > > > > > > ning.c > > > > > > @@ -82,6 +82,18 @@ static void > > > > > > intel_dp_read_lttpr_phy_caps(struct intel_dp > > > > > > *intel_dp, > > > > > > > > > > > > static bool > > > > > > intel_dp_read_lttpr_common_caps(struct intel_dp > > > > > > *intel_dp) > > > > > > { > > > > > > +struct drm_i915_private *i915 = > > > > > > dp_to_i915(intel_dp); > > > > > > + > > > > > > +if (intel_dp_is_edp(intel_dp)) > > > > > > +return false; > > > > > > + > > > > > > +/* > > > > > > + * Detecting LTTPRs must be avoided on platforms > > > > > > with > > > > > > an AUX timeout > > > > > > + * period < 3.2ms. (see DP Standard v2.0, > > > > > > 2.11.2, > > > > > > 3.6.6.1). > > > > > > + */ > > > > > > +if (INTEL_GEN(i915) < 10) > > > > > > +return false; > > > > > > + > > > > > > if (drm_dp_read_lttpr_common_caps(&intel_dp- > > > > > > >aux, > > > > > > intel_dp- > > > > > > > lttpr_common_caps) < 0) { > > > > > > memset(intel_dp->lttpr_common_caps, 0, > > > > > > @@ -127,9 +139,6 @@ int > > > > > > intel_dp_lttpr_init(struct intel_dp > > > > > > *intel_dp) > > > > > > bool ret; > > > > > > int i; > > > > > > > > > > > > -if (intel_dp_is_edp(intel_dp)) > > > > > > -return 0; > > > > > > - > > > > > > ret = intel_dp_read_lttpr_common_caps(intel_dp); > > > > > > if (!ret) > > > > > > return 0; > > > > > > -- > > > > > > 2.25.1 > > > > > > > > > > -- > > > > > Ville Syrjälä > > > > > Intel
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
-- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite!
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so.
Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +- .../drm/i915/display/intel_dp_link_training.c | 39 +++++++++++++------ .../drm/i915/display/intel_dp_link_training.h | 2 +- 3 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b6b5776f5a66..873684da0cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3711,9 +3711,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) { int ret;
- intel_dp_lttpr_init(intel_dp); - - if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) + if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) return false;
/* diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index c0e25c75c105..d8d90903226f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -35,6 +35,11 @@ intel_dp_dump_link_status(struct drm_device *drm, link_status[3], link_status[4], link_status[5]); }
+static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) +{ + memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); +} + static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) { intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - @@ -96,8 +101,7 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { - memset(intel_dp->lttpr_common_caps, 0, - sizeof(intel_dp->lttpr_common_caps)); + intel_dp_reset_lttpr_common_caps(intel_dp); return false; }
@@ -119,27 +123,37 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) }
/** - * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode + * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode * @intel_dp: Intel DP struct * - * Read the LTTPR common capabilities, switch to non-transparent link training - * mode if any is detected and read the PHY capabilities for all detected - * LTTPRs. In case of an LTTPR detection error or if the number of + * Read the LTTPR common and DPRX capabilities and switch to non-transparent + * link training mode if any is detected and read the PHY capabilities for all + * detected LTTPRs. In case of an LTTPR detection error or if the number of * LTTPRs is more than is supported (8), fall back to the no-LTTPR, * transparent mode link training mode. * * Returns: - * >0 if LTTPRs were detected and the non-transparent LT mode was set + * >0 if LTTPRs were detected and the non-transparent LT mode was set. The + * DPRX capabilities are read out. * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a - * detection failure and the transparent LT mode was set + * detection failure and the transparent LT mode was set. The DPRX + * capabilities are read out. + * <0 Reading out the DPRX capabilities failed. */ -int intel_dp_lttpr_init(struct intel_dp *intel_dp) +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { int lttpr_count; bool ret; int i;
ret = intel_dp_read_lttpr_common_caps(intel_dp); + + /* The DPTX shall read the DRPX caps after LTTPR detection. */ + if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { + intel_dp_reset_lttpr_common_caps(intel_dp); + return -EIO; + } + if (!ret) return 0;
@@ -182,7 +196,7 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp)
return lttpr_count; } -EXPORT_SYMBOL(intel_dp_lttpr_init); +EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);
static u8 dp_voltage_max(u8 preemph) { @@ -817,7 +831,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * TODO: Reiniting LTTPRs here won't be needed once proper connector * HW state readout is added. */ - int lttpr_count = intel_dp_lttpr_init(intel_dp); + int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); + + if (lttpr_count < 0) + return;
if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 6a1f76bd8c75..9cb7c28027f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -11,7 +11,7 @@ struct intel_crtc_state; struct intel_dp;
-int intel_dp_lttpr_init(struct intel_dp *intel_dp); +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so.
Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected.
v2: Add the actual version check.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +- .../drm/i915/display/intel_dp_link_training.c | 48 ++++++++++++++----- .../drm/i915/display/intel_dp_link_training.h | 2 +- 3 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b6b5776f5a66..873684da0cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3711,9 +3711,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) { int ret;
- intel_dp_lttpr_init(intel_dp); - - if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) + if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) return false;
/* diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index c0e25c75c105..5a821d644e9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -35,6 +35,11 @@ intel_dp_dump_link_status(struct drm_device *drm, link_status[3], link_status[4], link_status[5]); }
+static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) +{ + memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); +} + static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) { intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - @@ -96,8 +101,7 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) { - memset(intel_dp->lttpr_common_caps, 0, - sizeof(intel_dp->lttpr_common_caps)); + intel_dp_reset_lttpr_common_caps(intel_dp); return false; }
@@ -119,30 +123,49 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) }
/** - * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode + * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode * @intel_dp: Intel DP struct * - * Read the LTTPR common capabilities, switch to non-transparent link training - * mode if any is detected and read the PHY capabilities for all detected - * LTTPRs. In case of an LTTPR detection error or if the number of + * Read the LTTPR common and DPRX capabilities and switch to non-transparent + * link training mode if any is detected and read the PHY capabilities for all + * detected LTTPRs. In case of an LTTPR detection error or if the number of * LTTPRs is more than is supported (8), fall back to the no-LTTPR, * transparent mode link training mode. * * Returns: - * >0 if LTTPRs were detected and the non-transparent LT mode was set + * >0 if LTTPRs were detected and the non-transparent LT mode was set. The + * DPRX capabilities are read out. * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a - * detection failure and the transparent LT mode was set + * detection failure and the transparent LT mode was set. The DPRX + * capabilities are read out. + * <0 Reading out the DPRX capabilities failed. */ -int intel_dp_lttpr_init(struct intel_dp *intel_dp) +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { int lttpr_count; bool ret; int i;
ret = intel_dp_read_lttpr_common_caps(intel_dp); + + /* The DPTX shall read the DRPX caps after LTTPR detection. */ + if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { + intel_dp_reset_lttpr_common_caps(intel_dp); + return -EIO; + } + if (!ret) return 0;
+ /* + * The 0xF0000-0xF02FF range is only valid if the DPCD revision is + * at least 1.4. + */ + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) { + intel_dp_reset_lttpr_common_caps(intel_dp); + return 0; + } + lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); /* * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are @@ -182,7 +205,7 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp)
return lttpr_count; } -EXPORT_SYMBOL(intel_dp_lttpr_init); +EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);
static u8 dp_voltage_max(u8 preemph) { @@ -817,7 +840,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * TODO: Reiniting LTTPRs here won't be needed once proper connector * HW state readout is added. */ - int lttpr_count = intel_dp_lttpr_init(intel_dp); + int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); + + if (lttpr_count < 0) + return;
if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 6a1f76bd8c75..9cb7c28027f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -11,7 +11,7 @@ struct intel_crtc_state; struct intel_dp;
-int intel_dp_lttpr_init(struct intel_dp *intel_dp); +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
On Wed, Mar 17, 2021 at 09:01:49PM +0200, Imre Deak wrote:
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so.
Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected.
v2: Add the actual version check.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp.c | 4 +- .../drm/i915/display/intel_dp_link_training.c | 48 ++++++++++++++----- .../drm/i915/display/intel_dp_link_training.h | 2 +- 3 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b6b5776f5a66..873684da0cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3711,9 +3711,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) { int ret;
- intel_dp_lttpr_init(intel_dp);
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
- if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) return false;
/* diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index c0e25c75c105..5a821d644e9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -35,6 +35,11 @@ intel_dp_dump_link_status(struct drm_device *drm, link_status[3], link_status[4], link_status[5]); } +static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) +{
- memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
+}
static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) { intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - @@ -96,8 +101,7 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) {
memset(intel_dp->lttpr_common_caps, 0,sizeof(intel_dp->lttpr_common_caps));
intel_dp_reset_lttpr_common_caps(intel_dp);@@ -119,30 +123,49 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) } /**
- intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode
- intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
- @intel_dp: Intel DP struct
- Read the LTTPR common capabilities, switch to non-transparent link training
- mode if any is detected and read the PHY capabilities for all detected
- LTTPRs. In case of an LTTPR detection error or if the number of
- Read the LTTPR common and DPRX capabilities and switch to non-transparent
- link training mode if any is detected and read the PHY capabilities for all
- detected LTTPRs. In case of an LTTPR detection error or if the number of
- LTTPRs is more than is supported (8), fall back to the no-LTTPR,
- transparent mode link training mode.
- Returns:
DPRX capabilities are read out.- 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
detection failure and the transparent LT mode was set
detection failure and the transparent LT mode was set. The DPRX
capabilities are read out.*/
- <0 Reading out the DPRX capabilities failed.
-int intel_dp_lttpr_init(struct intel_dp *intel_dp) +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { int lttpr_count; bool ret; int i; ret = intel_dp_read_lttpr_common_caps(intel_dp);
- /* The DPTX shall read the DRPX caps after LTTPR detection. */
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);return -EIO;- }
- if (!ret) return 0;
- /*
* The 0xF0000-0xF02FF range is only valid if the DPCD revision is* at least 1.4.*/- if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
intel_dp_reset_lttpr_common_caps(intel_dp);return 0;- }
Slight chicken vs. egg I guess. Seems ok
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
- lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); /*
- Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
@@ -182,7 +205,7 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) return lttpr_count; } -EXPORT_SYMBOL(intel_dp_lttpr_init); +EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps); static u8 dp_voltage_max(u8 preemph) { @@ -817,7 +840,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * TODO: Reiniting LTTPRs here won't be needed once proper connector * HW state readout is added. */
- int lttpr_count = intel_dp_lttpr_init(intel_dp);
- int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
- if (lttpr_count < 0)
return;if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 6a1f76bd8c75..9cb7c28027f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -11,7 +11,7 @@ struct intel_crtc_state; struct intel_dp; -int intel_dp_lttpr_init(struct intel_dp *intel_dp); +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp); void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, -- 2.25.1
On Thu, Mar 18, 2021 at 07:57:22PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 09:01:49PM +0200, Imre Deak wrote:
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so.
Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected.
v2: Add the actual version check.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_dp.c | 4 +- .../drm/i915/display/intel_dp_link_training.c | 48 ++++++++++++++----- .../drm/i915/display/intel_dp_link_training.h | 2 +- 3 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b6b5776f5a66..873684da0cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3711,9 +3711,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) { int ret;
- intel_dp_lttpr_init(intel_dp);
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
- if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) return false;
/* diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index c0e25c75c105..5a821d644e9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -35,6 +35,11 @@ intel_dp_dump_link_status(struct drm_device *drm, link_status[3], link_status[4], link_status[5]); } +static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) +{
- memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
+}
static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) { intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - @@ -96,8 +101,7 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, intel_dp->lttpr_common_caps) < 0) {
memset(intel_dp->lttpr_common_caps, 0,sizeof(intel_dp->lttpr_common_caps));
intel_dp_reset_lttpr_common_caps(intel_dp);@@ -119,30 +123,49 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) } /**
- intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode
- intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
- @intel_dp: Intel DP struct
- Read the LTTPR common capabilities, switch to non-transparent link training
- mode if any is detected and read the PHY capabilities for all detected
- LTTPRs. In case of an LTTPR detection error or if the number of
- Read the LTTPR common and DPRX capabilities and switch to non-transparent
- link training mode if any is detected and read the PHY capabilities for all
- detected LTTPRs. In case of an LTTPR detection error or if the number of
- LTTPRs is more than is supported (8), fall back to the no-LTTPR,
- transparent mode link training mode.
- Returns:
DPRX capabilities are read out.- 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
detection failure and the transparent LT mode was set
detection failure and the transparent LT mode was set. The DPRX
capabilities are read out.*/
- <0 Reading out the DPRX capabilities failed.
-int intel_dp_lttpr_init(struct intel_dp *intel_dp) +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { int lttpr_count; bool ret; int i; ret = intel_dp_read_lttpr_common_caps(intel_dp);
- /* The DPTX shall read the DRPX caps after LTTPR detection. */
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);return -EIO;- }
- if (!ret) return 0;
- /*
* The 0xF0000-0xF02FF range is only valid if the DPCD revision is* at least 1.4.*/- if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
intel_dp_reset_lttpr_common_caps(intel_dp);return 0;- }
Slight chicken vs. egg I guess. Seems ok
Yes, reading 0xF0000-0xF0007 has a side effect and I suppose the LTTPRs could change something in the returned DPRX caps, depending on whether the read happened or not.
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
- lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); /*
- Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
@@ -182,7 +205,7 @@ int intel_dp_lttpr_init(struct intel_dp *intel_dp) return lttpr_count; } -EXPORT_SYMBOL(intel_dp_lttpr_init); +EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps); static u8 dp_voltage_max(u8 preemph) { @@ -817,7 +840,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * TODO: Reiniting LTTPRs here won't be needed once proper connector * HW state readout is added. */
- int lttpr_count = intel_dp_lttpr_init(intel_dp);
- int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
- if (lttpr_count < 0)
return;if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 6a1f76bd8c75..9cb7c28027f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -11,7 +11,7 @@ struct intel_crtc_state; struct intel_dp; -int intel_dp_lttpr_init(struct intel_dp *intel_dp); +int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp); void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, -- 2.25.1
-- Ville Syrjälä Intel
By the specification the 0xF0000 - 0xF02FF range is only valid if the LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support otherwise.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com --- .../gpu/drm/i915/display/intel_dp_link_training.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d8d90903226f..d92eb192c89d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) return false;
if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, - intel_dp->lttpr_common_caps) < 0) { - intel_dp_reset_lttpr_common_caps(intel_dp); - return false; - } + intel_dp->lttpr_common_caps) < 0) + goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "LTTPR common capabilities: %*ph\n", (int)sizeof(intel_dp->lttpr_common_caps), intel_dp->lttpr_common_caps);
+ /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ + if (intel_dp->lttpr_common_caps[0] < 0x14) + goto reset_caps; + return true; + +reset_caps: + intel_dp_reset_lttpr_common_caps(intel_dp); + return false; }
static bool
On Wed, Mar 17, 2021 at 08:49:01PM +0200, Imre Deak wrote:
By the specification the 0xF0000 - 0xF02FF range is only valid if the LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support otherwise.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
.../gpu/drm/i915/display/intel_dp_link_training.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d8d90903226f..d92eb192c89d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) return false; if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
intel_dp->lttpr_common_caps) < 0) {intel_dp_reset_lttpr_common_caps(intel_dp);return false;- }
intel_dp->lttpr_common_caps) < 0)goto reset_caps;
BTW just noticed this oddball thing in the spec: "DPTX shall read specific registers within the LTTPR field (DPCD Addresses F0000h through F0004h; see Table 2-198) to determine whether any LTTPR(s) are present and if so, how many. This read shall be in the form of a 5-byte native AUX Read transaction."
Why exactly 5 bytes? I have no idea. Doesn't really make sense. Just wondering if we really need to respect that and some LTTPRs would fsck things up if we read more...
Anyways Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "LTTPR common capabilities: %*ph\n", (int)sizeof(intel_dp->lttpr_common_caps), intel_dp->lttpr_common_caps);
- /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
- if (intel_dp->lttpr_common_caps[0] < 0x14)
goto reset_caps;- return true;
+reset_caps:
- intel_dp_reset_lttpr_common_caps(intel_dp);
- return false;
} static bool -- 2.25.1
On Thu, Mar 18, 2021 at 08:00:10PM +0200, Ville Syrjälä wrote:
On Wed, Mar 17, 2021 at 08:49:01PM +0200, Imre Deak wrote:
By the specification the 0xF0000 - 0xF02FF range is only valid if the LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support otherwise.
Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training") Cc: stable@vger.kernel.org # v5.11 Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Imre Deak imre.deak@intel.com
.../gpu/drm/i915/display/intel_dp_link_training.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d8d90903226f..d92eb192c89d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) return false; if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
intel_dp->lttpr_common_caps) < 0) {intel_dp_reset_lttpr_common_caps(intel_dp);return false;- }
intel_dp->lttpr_common_caps) < 0)goto reset_caps;BTW just noticed this oddball thing in the spec: "DPTX shall read specific registers within the LTTPR field (DPCD Addresses F0000h through F0004h; see Table 2-198) to determine whether any LTTPR(s) are present and if so, how many. This read shall be in the form of a 5-byte native AUX Read transaction."
Why exactly 5 bytes? I have no idea. Doesn't really make sense. Just wondering if we really need to respect that and some LTTPRs would fsck things up if we read more...
I pointed this out to spec people and the new version (2.1) will require this to be 8 bytes. But yes, I do hope no existing ones depend on this being 5 bytes.
Anyways Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "LTTPR common capabilities: %*ph\n", (int)sizeof(intel_dp->lttpr_common_caps), intel_dp->lttpr_common_caps);
- /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
- if (intel_dp->lttpr_common_caps[0] < 0x14)
goto reset_caps;- return true;
+reset_caps:
- intel_dp_reset_lttpr_common_caps(intel_dp);
- return false;
} static bool -- 2.25.1
-- Ville Syrjälä Intel
linux-stable-mirror@lists.linaro.org
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Almahallawy, Khaled -
Imre Deak -
Lyude Paul -
Ville Syrjälä