Re: [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks

On Tue, May 20, 2025 at 11:07:42AM +0200, Krzysztof Kozlowski wrote:

On SM8750 the setting rate of pixel and byte clocks, while the parent DSI PHY PLL, fails with:

disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.

DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in CMN_CTRL_0 asserted.

Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is enabled during rate changes.

Cc: stable@vger.kernel.org Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller") Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org

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Changes in v6:

1. Add CLK_OPS_PARENT_ENABLE also to pclk1, pclk2 and byte1.
2. Add Fixes tag and cc-stable

Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com