From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit 23c81e7a7e5204a08b553d07362d3082926663b8 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Fixes: 913b86468674 ("iio: adc: Add TI ADC128S052") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-33-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/adc/ti-adc128s052.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index 8e7adec87755..622fd384983c 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -29,7 +29,7 @@ struct adc128 { struct regulator *reg; struct mutex lock;
- u8 buffer[2] ____cacheline_aligned; + u8 buffer[2] __aligned(IIO_DMA_MINALIGN); };
static int adc128_adc_conversion(struct adc128 *adc, u8 channel)