[PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts

The "PolarFire SoC MSS Technical Reference Manual" documents the following PLIC interrupts:

1 - L2 Cache Controller Signals when a metadata correction event occurs 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs 3 - L2 Cache Controller Signals when a data correction event occurs 4 - L2 Cache Controller Signals when an uncorrectable data event occurs

This differs from the SiFive FU540 which only has three L2 cache related interrupts.

The sequence in the device tree is defined by an enum:

enum {         DIR_CORR = 0,         DATA_CORR,         DATA_UNCORR,         DIR_UNCORR, };

So the correct sequence of the L2 cache interrupts is

interrupts = <1>, <3>, <4>, <2>;

Fixes: e35b07a7df9b ("riscv: dts: microchip: mpfs: Group tuples in interrupt properties") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Cc: Conor Dooley conor.dooley@microchip.com Cc: stable@vger.kernel.org Signed-off-by: Heinrich Schuchardt heinrich.schuchardt@canonical.com --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 496d3b7642bd..ec1de6344be9 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -169,7 +169,7 @@ cctrllr: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic>; - interrupts = <1>, <2>, <3>; + interrupts = <1>, <3>, <4>, <2>; };

clint: clint@2000000 {