6.13-stable review patch. If anyone has any objections, please let me know.
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From: Josua Mayer josua@solid-run.com
[ Upstream commit 09cdb973afa7a18ce8e66807daff94609cc4b8a4 ]
Marvell CN913x platforms use common phy framework for configuring and linking serdes lanes according to their usage. Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY nodes.
CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1 respectively. Devicetree however wrongly links from these ports to the comphy of CP0.
Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1, cp1_eth2.
Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board") Signed-off-by: Josua Mayer josua@solid-run.com Signed-off-by: Gregory CLEMENT gregory.clement@bootlin.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts index b1ea7dcaed17d..47234d0858dd2 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -435,7 +435,7 @@ managed = "in-band-status"; phy-mode = "sgmii"; phy = <&cp1_phy0>; - phys = <&cp0_comphy3 1>; + phys = <&cp1_comphy3 1>; status = "okay"; };
@@ -444,7 +444,7 @@ managed = "in-band-status"; phy-mode = "sgmii"; phy = <&cp1_phy1>; - phys = <&cp0_comphy5 2>; + phys = <&cp1_comphy5 2>; status = "okay"; };