From: Matt Roper matthew.d.roper@intel.com
[ Upstream commit 33c25354939099b76ecb6c82d1c7c50400fbcca6 ]
MCR range tables use the final MMIO offset of a register (including the 0x380000 GSI offset when applicable). Since the i915_mcr_reg_t passed as a parameter during steering lookup does not include the GSI offset, we need to add it back in for GSI registers before searching the tables.
Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") Signed-off-by: Matt Roper matthew.d.roper@intel.com Reviewed-by: Radhakrishna Sripada radhakrishna.sripada@intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20230214001906.1477370-1-matth... (cherry picked from commit d6683bbe70d4cdbf3da6acecf7d569cc6f0b4382) Signed-off-by: Jani Nikula jani.nikula@intel.com Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index 58ea3325bbdaa..fa2b9c48f39b2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -464,12 +464,15 @@ static bool reg_needs_read_steering(struct intel_gt *gt, i915_mcr_reg_t reg, enum intel_steering_type type) { - const u32 offset = i915_mmio_reg_offset(reg); + u32 offset = i915_mmio_reg_offset(reg); const struct intel_mmio_range *entry;
if (likely(!gt->steering_table[type])) return false;
+ if (IS_GSI_REG(offset)) + offset += gt->uncore->gsi_offset; + for (entry = gt->steering_table[type]; entry->end; entry++) { if (offset >= entry->start && offset <= entry->end) return true;