On Sat, Apr 19, 2025 at 8:52 PM Marcelo Schmitt marcelo.schmitt1@gmail.com wrote:
On 04/19, Gabriel Shahrouzi wrote:
Implement the settling cycles encoding as specified in the AD5933 datasheet, Table 13 ("Number of Settling Times Cycles Register"). The previous logic did not correctly translate the user-requested effective cycle count into the required 9-bit base + 2-bit multiplier format (D10..D0) for values exceeding 511.
Hmm, the above description should probably go on the refactoring patch I think. Otherwise looks good.
You're right - will update that for v4. I don't think my description was accurate either since the old logic did correctly map the cycle counts to the correct bits. It just didn't use the correct mask.
Reviewed-by: Marcelo Schmitt marcelo.schmitt1@gmail.com
Clamp the user input for out_altvoltage0_settling_cycles to the maximum effective value of 2044 cycles (511 * 4x multiplier).
Fixes: f94aa354d676 ("iio: impedance-analyzer: New driver for AD5933/4 Impedance Converter, Network Analyzer") Cc: stable@vger.kernel.org Signed-off-by: Gabriel Shahrouzi gshahrouzi@gmail.com
Changes in v3: - Only include fix (remove refactoring which will be its own separate patch). Changes in v2: - Fix spacing in comment around '+'. - Define mask and values for settling cycle multipliers.