The patch below does not apply to the 5.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to stable@vger.kernel.org.
Possible dependencies:
67bf6493449b ("x86/resctrl: Fix min_cbm_bits for AMD") 2b8dd4ab65da ("x86/resctrl: Calculate the index from the configuration type") 2e7df368fc92 ("x86/resctrl: Apply offset correction when config is staged") f07e9d025057 ("x86/resctrl: Add a helper to read a closid's configuration") 2e6678195d59 ("x86/resctrl: Rename update_domains() to resctrl_arch_update_domains()") 75408e43509e ("x86/resctrl: Allow different CODE/DATA configurations to be staged") e8f7282552b9 ("x86/resctrl: Group staged configuration into a separate struct") 1c290682c0c9 ("x86/resctrl: Pass the schema to resctrl filesystem functions") eb6f31876941 ("x86/resctrl: Add resctrl_arch_get_num_closid()") 3183e87c1b79 ("x86/resctrl: Store the effective num_closid in the schema") 331ebe4c4349 ("x86/resctrl: Walk the resctrl schema list instead of an arch list") 208ab16847c5 ("x86/resctrl: Label the resources with their configuration type") f2594492308d ("x86/resctrl: Pass the schema in info dir's private pointer") cdb9ebc91784 ("x86/resctrl: Add a separate schema list for resctrl") 792e0f6f789b ("x86/resctrl: Split struct rdt_domain") 63c8b1231929 ("x86/resctrl: Split struct rdt_resource") fd2afa70eff0 ("x86/resctrl: Fix kernel-doc in internal.h") 8ba27ae36b41 ("Merge tag 'x86_cache_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 67bf6493449b09590f9f71d7df29efb392b12d25 Mon Sep 17 00:00:00 2001 From: Babu Moger babu.moger@amd.com Date: Tue, 27 Sep 2022 15:16:29 -0500 Subject: [PATCH] x86/resctrl: Fix min_cbm_bits for AMD
AMD systems support zero CBM (capacity bit mask) for cache allocation. That is reflected in rdt_init_res_defs_amd() by:
r->cache.arch_has_empty_bitmaps = true;
However given the unified code in cbm_validate(), checking for:
val == 0 && !arch_has_empty_bitmaps
is not enough because of another check in cbm_validate():
if ((zero_bit - first_bit) < r->cache.min_cbm_bits)
The default value of r->cache.min_cbm_bits = 1.
Leading to:
$ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=0 > schemata -bash: echo: write error: Invalid argument $ cat /sys/fs/resctrl/info/last_cmd_status Need at least 1 bits in the mask
Initialize the min_cbm_bits to 0 for AMD. Also, remove the default setting of min_cbm_bits and initialize it separately.
After the fix:
$ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=0 > schemata $ cat /sys/fs/resctrl/info/last_cmd_status ok
Fixes: 316e7f901f5a ("x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps") Co-developed-by: Stephane Eranian eranian@google.com Signed-off-by: Stephane Eranian eranian@google.com Signed-off-by: Babu Moger babu.moger@amd.com Signed-off-by: Borislav Petkov bp@suse.de Reviewed-by: Ingo Molnar mingo@kernel.org Reviewed-by: James Morse james.morse@arm.com Reviewed-by: Reinette Chatre reinette.chatre@intel.com Reviewed-by: Fenghua Yu fenghua.yu@intel.com Cc: stable@vger.kernel.org Link: https://lore.kernel.org/lkml/20220517001234.3137157-1-eranian@google.com
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index de62b0b87ced..3266ea36667c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3, .name = "L3", .cache_level = 3, - .cache = { - .min_cbm_bits = 1, - }, .domains = domain_init(RDT_RESOURCE_L3), .parse_ctrlval = parse_cbm, .format_str = "%d=%0*x", @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2, .name = "L2", .cache_level = 2, - .cache = { - .min_cbm_bits = 1, - }, .domains = domain_init(RDT_RESOURCE_L2), .parse_ctrlval = parse_cbm, .format_str = "%d=%0*x", @@ -836,6 +830,7 @@ static __init void rdt_init_res_defs_intel(void) r->cache.arch_has_sparse_bitmaps = false; r->cache.arch_has_empty_bitmaps = false; r->cache.arch_has_per_cpu_cfg = false; + r->cache.min_cbm_bits = 1; } else if (r->rid == RDT_RESOURCE_MBA) { hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; hw_res->msr_update = mba_wrmsr_intel; @@ -856,6 +851,7 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_sparse_bitmaps = true; r->cache.arch_has_empty_bitmaps = true; r->cache.arch_has_per_cpu_cfg = true; + r->cache.min_cbm_bits = 0; } else if (r->rid == RDT_RESOURCE_MBA) { hw_res->msr_base = MSR_IA32_MBA_BW_BASE; hw_res->msr_update = mba_wrmsr_amd;