The MIPS FPU may have 2 mode: FR=0: MIPS I style, odd-FPR can only be single, and even-FPR can be double. FR=1: all 32 FPR can be double.
The binary may have 3 mode: FP32: can only work with FR=0 mode FPXX: can work with both FR=0 and FR=1 mode. FP64: can only work with FR=1 mode
Some binary, for example the output of golang, may be mark as FPXX, while in fact they are FP32.
Currently, FR=1 mode is used for all FPXX binary, it makes some wrong behivour of the binaries. Since FPXX binary can work with both FR=1 and FR=0, we force it to use FR=0.
Reference:
https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/...
https://go-review.googlesource.com/c/go/+/239217 https://go-review.googlesource.com/c/go/+/237058
Signed-off-by: YunQiang Su yunqiang.su@cipunited.com Cc: stable@vger.kernel.org # 4.19+
v5->v6: Rollback to V3, aka remove config option.
v4->v5: Fix CONFIG_MIPS_O32_FPXX_USE_FR0 usage: if -> ifdef
v3->v4: introduce a config option: CONFIG_MIPS_O32_FPXX_USE_FR0
v2->v3: commit message: add Signed-off-by and Cc to stable.
v1->v2: Fix bad commit message: in fact, we are switching to FR=0 --- arch/mips/kernel/elf.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 7b045d2a0b51..d1aa907e9864 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -234,9 +234,10 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU * instructions so we don't care about the mode. We will simply use * the one preferred by the hardware. In fpxx case, that ABI can - * handle both FR=1 and FR=0, so, again, we simply choose the one - * preferred by the hardware. Next, if we only use single-precision - * FPU instructions, and the default ABI FPU mode is not good + * handle both FR=1 and FR=0. Here, we may need to use FR=0, because + * some binaries may be mark as FPXX by mistake (ie, output of golang). + * - If we only use single-precision FPU instructions, + * and the default ABI FPU mode is not good * (ie single + any ABI combination), we set again the FPU mode to the * one is preferred by the hardware. Next, if we know that the code * will only use single-precision instructions, shown by single being @@ -248,8 +249,9 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, */ if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) state->overall_fp_mode = FP_FRE; - else if ((prog_req.fr1 && prog_req.frdefault) || - (prog_req.single && !prog_req.frdefault)) + else if (prog_req.fr1 && prog_req.frdefault) + state->overall_fp_mode = FP_FR0; + else if (prog_req.single && !prog_req.frdefault) /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) && cpu_has_mips_r2_r6) ?