On Fri, 17 Oct 2025 18:32:53 +0200, Niklas Cassel wrote:
The L1 substates support requires additional steps to work, namely: -Proper handling of the CLKREQ# sideband signal. (It is mostly handled by hardware, but software still needs to set the clkreq fields in the PCIE_CLIENT_POWER_CON register to match the hardware implementation.) -Program the frequency of the aux clock into the DSP_PCIE_PL_AUX_CLK_FREQ_OFF register. (During L1 substates the core_clk is turned off and the aux_clk is used instead.)
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Applied, thanks!
[1/1] PCI: dw-rockchip: Prevent advertising L1 Substates support commit: 40331c63e7901a2cc75ce6b5d24d50601efb833d
Best regards,