On Fri, Mar 08, 2024 at 09:22:16PM +0100, Andi Shyti wrote:
The hardware should not dynamically balance the load between CCS engines. Wa_14019159160 recommends disabling it across all platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") Signed-off-by: Andi Shyti andi.shyti@linux.intel.com Cc: Chris Wilson chris.p.wilson@linux.intel.com Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Matt Roper matthew.d.roper@intel.com Cc: stable@vger.kernel.org # v6.2+
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 50962cfd1353..cf709f6c05ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1478,6 +1478,7 @@ #define GEN12_RCU_MODE _MMIO(0x14800) #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
Nitpick: we usually order register bits in descending order. Aside from that,
Reviewed-by: Matt Roper matthew.d.roper@intel.com
although I still hope our architects will push through a formal documentation update for this.
Matt
#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 25413809b9dc..4865eb5ca9c9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -51,7 +51,8 @@
- registers belonging to BCS, VCS or VECS should be implemented in
- xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
- engine's MMIO range but that are part of of the common RCS/CCS reset domain
- should be implemented in general_render_compute_wa_init().
- should be implemented in general_render_compute_wa_init(). The settings
- about the CCS load balancing should be added in ccs_engine_wa_mode().
- GT workarounds: the list of these WAs is applied whenever these registers
- revert to their default values: on GPU reset, suspend/resume [1]_, etc.
@@ -2854,6 +2855,22 @@ add_render_compute_tuning_settings(struct intel_gt *gt, wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); } +static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) +{
- struct intel_gt *gt = engine->gt;
- if (!IS_DG2(gt->i915))
return;- /*
* Wa_14019159160: This workaround, along with others, leads to* significant challenges in utilizing load balancing among the* CCS slices. Consequently, an architectural decision has been* made to completely disable automatic CCS load balancing.*/- wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
+}
/*
- The workarounds in this function apply to shared registers in
- the general render reset domain that aren't tied to a
@@ -3004,8 +3021,10 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal * to a single RCS/CCS engine's workaround list since * they're reset as part of the general render domain reset. */
- if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
- if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) { general_render_compute_wa_init(engine, wal);
ccs_engine_wa_mode(engine, wal);- }
if (engine->class == COMPUTE_CLASS) ccs_engine_wa_init(engine, wal); -- 2.43.0