From: Sridevi Arvindekar sarvinde@amd.com
[ Upstream commit 0bf6b216d4783cb51f9af05a49d3cce4fc22dc24 ]
[Why/How] Call power gating routine only if it is defined.
Reviewed-by: Alvin Lee alvin.lee2@amd.com Signed-off-by: Sridevi Arvindekar sarvinde@amd.com Signed-off-by: Ivan Lipski ivan.lipski@amd.com Tested-by: Dan Wheeler daniel.wheeler@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES – Adding the NULL guard in `dcn20_fpga_init_hw` keeps the FPGA init path from dereferencing a deliberately cleared power‑gating hook on Navi12.
- Root cause is that Navi12 forces `dc->hwseq->funcs.enable_power_gating_plane = NULL` to avoid the unwanted register programming (`drivers/gpu/drm/amd/display/dc/resourc e/dcn20/dcn20_resource.c:2728`), so the unguarded call in the FPGA init routine dereferenced a NULL function pointer and crashed the test path (`drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c:3132` before this fix). - The patch simply checks the pointer before calling, matching the pattern already used in other init flows such as `dcn10_init_hw` and newer DCN generations, so functional behaviour is unchanged when the hook exists and we correctly skip it when it is absent. - Impacted hardware (Navi12/DCN2.0) ships in currently supported stable kernels, and the unfixed bug is an outright NULL dereference, so users running the FPGA/diagnostic init sequence still hit a crash today. - Change is localized, does not pull in other dependencies, and aligns with existing defensive guards elsewhere in the display stack, making regression risk very low.
Suggested follow-up: 1) Run the relevant FPGA/Navi12 display init test (or the scenario that originally crashed) on the target stable branch to confirm the NULL dereference is gone.
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 9d3946065620a..f7b72b24b7509 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3129,7 +3129,8 @@ void dcn20_fpga_init_hw(struct dc *dc) res_pool->dccg->funcs->dccg_init(res_pool->dccg);
//Enable ability to power gate / don't force power on permanently - hws->funcs.enable_power_gating_plane(hws, true); + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(hws, true);
// Specific to FPGA dccg and registers REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);