From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit ae6eeb534924ecc2afd5a394964fd6de0ca54d39 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Fixes tag is inaccurate but unlikely anyone will backport this beyond that point so I haven't chased the history futher than 2013.
Fixes: 3c80372dae17 ("staging:iio:adis16080: be16 cleanups") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-73-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/gyro/adis16080.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/gyro/adis16080.c b/drivers/iio/gyro/adis16080.c index acef59d822b1..14b3abf6dce9 100644 --- a/drivers/iio/gyro/adis16080.c +++ b/drivers/iio/gyro/adis16080.c @@ -45,7 +45,7 @@ struct adis16080_state { const struct adis16080_chip_info *info; struct mutex lock;
- __be16 buf ____cacheline_aligned; + __be16 buf __aligned(IIO_DMA_MINALIGN); };
static int adis16080_read_sample(struct iio_dev *indio_dev,