On Mon, 09 Jun 2025 20:58:05 -0300, Jason Gunthorpe wrote:
The AMD IOMMU documentation seems pretty clear that the V2 table follows the normal CPU expectation of sign extension. This is shown in
Figure 25: AMD64 Long Mode 4-Kbyte Page Address Translation
Where bits Sign-Extend [63:57] == [56]. This is typical for x86 which would have three regions in the page table: lower, non-canonical, upper.
[...]
Applied to iommu (amd/amd-vi), thanks!
[1/1] iommu/amd: Fix geometry.aperture_end for V2 tables https://git.kernel.org/iommu/c/8637afa79cfa
Cheers,