4.17-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marc Zyngier marc.zyngier@arm.com
[ Upstream commit 82f499c8811149069ec958b72a86643a7a289b25 ]
Enabling LPIs was made a lot stricter recently, by checking that they are disabled before enabling them. By doing so, the CPU hotplug case was missed altogether, which leaves LPIs enabled on hotplug off (expecting the CPU to eventually come back), and won't write a different value anyway on hotplug on.
So skip that check if that particular case is detected
Fixes: 6eb486b66a30 ("irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling") Reported-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Marc Zyngier marc.zyngier@arm.com Signed-off-by: Thomas Gleixner tglx@linutronix.de Tested-by: Sumit Garg sumit.garg@linaro.org Cc: Jason Cooper jason@lakedaemon.net Cc: Alexandre Belloni alexandre.belloni@bootlin.com Cc: Yang Yingliang yangyingliang@huawei.com Link: https://lkml.kernel.org/r/20180622095254.5906-8-marc.zyngier@arm.com Signed-off-by: Sasha Levin alexander.levin@microsoft.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/irqchip/irq-gic-v3-its.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
--- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3405,6 +3405,16 @@ static int redist_disable_lpis(void) u64 timeout = USEC_PER_SEC; u64 val;
+ /* + * If coming via a CPU hotplug event, we don't need to disable + * LPIs before trying to re-enable them. They are already + * configured and all is well in the world. Detect this case + * by checking the allocation of the pending table for the + * current CPU. + */ + if (gic_data_rdist()->pend_page) + return 0; + if (!gic_rdists_supports_plpis()) { pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); return -ENXIO;