On Wed, Jun 08, 2022 at 10:19:01AM +0100, Russell King (Oracle) wrote:
On Wed, Jun 08, 2022 at 10:54:48AM +0200, Thorsten Leemhuis wrote:
On 07.06.22 13:58, Eric Schikschneit wrote:
I am limited by the availability of the preempt-rt kernels that are available on the yocto project. The newest kernel I see listed is 5.15.44 on: https://git.yoctoproject.org/linux-yocto/
Well, it's up to Russel if that is enough for him, as he authored c859e0d479b3 ("gpio: omap: ensure irq is enabled before wakeup") and thus should look into this regression.
I've already made it clear that is something I can no longer do; I no longer have the knowledge, nor do I have the hardware to test for this regression.
There's a lot of debugging that needs to be done that can only be done by the reporter to work out exactly what is going on. Most of what is below is guess work - as I say, I don't have the knowledge, but what follows is based on what would be a sensible investigation approach.
As I understand it having *briefly* looked at what I guess is the right SPI code - I don't know - I'm guessing the CS lines are manually controlled by the SPI driver via the GPIO layer.
If that is correct, the SPI driver must be itself deasserting the CS line at the inappropriate point. This means the reporter needs to locate where that is happening, and work out why the driver is doing that. dump_stack() can be inserted at the appropriate point(s) to get a stack trace to show the call path, which may or may not reveal how we got there.
Also, we have no idea what the SPI device is, or how the driver for the SPI device is using the SPI subsystem. Are there two separate transfers being issued to the SPI subsystem, and is the CS signal being deasserted between those two transfers?
If that is the case, deasserting the CS signal between the two transfers seems to me to be entirely reasonable - as once a transfer has completed, the SPI bus _could_ be used to access another peripheral before the second transfer is acted upon. If this is the case, then this commit has revealed a latent bug.
If CS is deasserted between two separate SPI transactions, but the chip must not see CS deasserted, then that would be a bug in the SPI device driver and have nothing to do with the GPIO layer. The change in the GPIO code would have revealed a latent bug in the SPI side of things (maybe the SPI device driver.)
There is just so much that is unknown here, and there is nothing I can do here locally to debug this.