On Thu, 03 Oct 2024 19:28:59 +0200 Angelo Dureghello adureghello@baylibre.com wrote:
From: Angelo Dureghello adureghello@baylibre.com
Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.
Both generic DAC and ad3552r DAC IPs docs are reporting bit 5 for it.
Reorder to come before the previous patch. This want's backporting. The renames are good but too noisy to backport if we can avoid it.
Jonathan
Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip Fixes: 4e3949a192e4 ("iio: dac: add support for AXI DAC IP core") Cc: stable@vger.kernel.org Signed-off-by: Angelo Dureghello adureghello@baylibre.com Reviewed-by: Nuno Sa nuno.sa@analog.com
drivers/iio/dac/adi-axi-dac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index e83f70465b46..04193a98616e 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -46,7 +46,7 @@ #define AXI_DAC_CNTRL_1_REG 0x0044 #define AXI_DAC_CNTRL_1_SYNC BIT(0) #define AXI_DAC_CNTRL_2_REG 0x0048 -#define ADI_DAC_CNTRL_2_R1_MODE BIT(4) +#define ADI_DAC_CNTRL_2_R1_MODE BIT(5) #define AXI_DAC_DRP_STATUS_REG 0x0074 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)