6.8-stable review patch. If anyone has any objections, please let me know.
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From: Ville Syrjälä ville.syrjala@linux.intel.com
commit 4a36e46df7aa781c756f09727d37dc2783f1ee75 upstream.
All joined pipes share the same transcoder/timing generator. Currently we just do the commits per-pipe, which doesn't really work if we need to change the timings at the same time. For now just disable live M/N updates when bigjoiner is needed.
Cc: stable@vger.kernel.org Tested-by: Vidya Srinivas vidya.srinivas@intel.com Reviewed-by: Arun R Murthy arun.r.murthy@intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-5-ville.s... Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com (cherry picked from commit ef79820db723a2a7c229a7251c12859e7e25a247) Signed-off-by: Rodrigo Vivi rodrigo.vivi@intel.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2756,7 +2756,11 @@ intel_dp_drrs_compute_config(struct inte intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); int pixel_clock;
- if (has_seamless_m_n(connector)) + /* + * FIXME all joined pipes share the same transcoder. + * Need to account for that when updating M/N live. + */ + if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes) pipe_config->update_m_n = true;
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {