You're right. DC5 could disrupt GMBUS. We forgot to add a note on GMBUS when it got moved under DMC domain in GLK and BXT/APL. I'll take care of that.
-----Original Message----- From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] Sent: Monday, 11 December, 2017 11:03 AM To: Pandiyan, Dhinakaran dhinakaran.pandiyan@intel.com Cc: intel-gfx@lists.freedesktop.org; stable@vger.kernel.org; Runyan, Arthur J arthur.j.runyan@intel.com Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK
On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS lives in PG1 so DC off is all we need.
Just so that I understand this correctly. DMC is expected to take care of managing power for GMBUS transfers without the driver explicitly turning on/off the power well 1 but it isn't. Do you know if this is a DMC regression?
No idea. The docs don't seem to even mention DMC and GMBUS in the same sentence. But since DP AUX needs DC off I don't see why GMBUS would be all that different.
And with bit banging I would be somewhat surprised if DMC could maintain the state of the pins while in DC5. Although I suppose it might be possible that the hw automagically prevents DC5 when we're driving any of the pins.
Art?
Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 96ab74f3d101..522e0a63090f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \