The patch below does not apply to the 4.14-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to stable@vger.kernel.org.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-4.14.y git checkout FETCH_HEAD git cherry-pick -x ce0b15d11ad837fbacc5356941712218e38a0a83 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to 'stable@vger.kernel.org' --in-reply-to '2023052616-audibly-grinning-73b4@gregkh' --subject-prefix 'PATCH 4.14.y' HEAD^..
Possible dependencies:
ce0b15d11ad8 ("x86/mm: Avoid incomplete Global INVLPG flushes") 6cff64b86aaa ("x86/mm: Use INVPCID for __native_flush_tlb_single()") 6fd166aae78c ("x86/mm: Use/Fix PCID to optimize user/kernel switches") 48e111982cda ("x86/mm: Abstract switching CR3") 2ea907c4fe7b ("x86/mm: Allow flushing for future ASID switches") aa8c6248f8c7 ("x86/mm/pti: Add infrastructure for page table isolation") 8a09317b895f ("x86/mm/pti: Prepare the x86/entry assembly code for entry/exit CR3 switching") 613e396bc0d4 ("init: Invoke init_espfix_bsp() from mm_init()") 1a3b0caeb77e ("x86/mm: Create asm/invpcid.h") dd95f1a4b5ca ("x86/mm: Put MMU to hardware ASID translation in one place") cb0a9144a744 ("x86/mm: Remove hard-coded ASID limit checks") 50fb83a62cf4 ("x86/mm: Move the CR3 construction functions to tlbflush.h") 3f67af51e56f ("x86/mm: Add comments to clarify which TLB-flush functions are supposed to flush what") 23cb7d46f371 ("x86/microcode: Dont abuse the TLB-flush interface") c482feefe1ae ("x86/entry/64: Make cpu_entry_area.tss read-only") 0f9a48100fba ("x86/entry: Clean up the SYSENTER_stack code") 7fbbd5cbebf1 ("x86/entry/64: Remove the SYSENTER stack canary") 40e7f949e0d9 ("x86/entry/64: Move the IST stacks into struct cpu_entry_area") 3386bc8aed82 ("x86/entry/64: Create a per-CPU SYSCALL entry trampoline") 3e3b9293d392 ("x86/entry/64: Return to userspace from the trampoline stack")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 From: Dave Hansen dave.hansen@linux.intel.com Date: Tue, 16 May 2023 12:24:25 -0700 Subject: [PATCH] x86/mm: Avoid incomplete Global INVLPG flushes
The INVLPG instruction is used to invalidate TLB entries for a specified virtual address. When PCIDs are enabled, INVLPG is supposed to invalidate TLB entries for the specified address for both the current PCID *and* Global entries. (Note: Only kernel mappings set Global=1.)
Unfortunately, some INVLPG implementations can leave Global translations unflushed when PCIDs are enabled.
As a workaround, never enable PCIDs on affected processors.
I expect there to eventually be microcode mitigations to replace this software workaround. However, the exact version numbers where that will happen are not known today. Once the version numbers are set in stone, the processor list can be tweaked to only disable PCIDs on affected processors with affected microcode.
Note: if anyone wants a quick fix that doesn't require patching, just stick 'nopcid' on your kernel command-line.
Signed-off-by: Dave Hansen dave.hansen@linux.intel.com Reviewed-by: Thomas Gleixner tglx@linutronix.de Cc: stable@vger.kernel.org
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 3cdac0f0055d..8192452d1d2d 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -9,6 +9,7 @@ #include <linux/sched/task.h>
#include <asm/set_memory.h> +#include <asm/cpu_device_id.h> #include <asm/e820/api.h> #include <asm/init.h> #include <asm/page.h> @@ -261,6 +262,24 @@ static void __init probe_page_size_mask(void) } }
+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ + .family = 6, \ + .model = _model, \ + } +/* + * INVLPG may not properly flush Global entries + * on these CPUs when PCIDs are enabled. + */ +static const struct x86_cpu_id invlpg_miss_ids[] = { + INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + {} +}; + static void setup_pcid(void) { if (!IS_ENABLED(CONFIG_X86_64)) @@ -269,6 +288,12 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return;
+ if (x86_match_cpu(invlpg_miss_ids)) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; + } + if (boot_cpu_has(X86_FEATURE_PGE)) { /* * This can't be cr4_set_bits_and_update_boot() -- the