On 03/09/2025 14:37, Abel Vesa wrote:
On X Elite platform, the eDP PHY uses one more clock called refclk. Add it to the schema.
Cc: stable@vger.kernel.org # v6.10 Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") Signed-off-by: Abel Vesa abel.vesa@linaro.org
.../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -37,12 +37,15 @@ properties: - description: PLL register block clocks:
- maxItems: 2
- minItems: 2
- maxItems: 3
clock-names:
- minItems: 2 items:
- const: aux
- const: cfg_ahb
- const: refclk
Name is: "ref"
"#clock-cells": const: 1 @@ -64,6 +67,29 @@ required:
- "#clock-cells"
- "#phy-cells"
+allOf:
- if:
properties:compatible:enum:- qcom,x1e80100-dp-phy- then:
properties:clocks:minItems: 3
That's an ABI break, so you need to explain it and mention the impact. Reason that there is one more clock, but everything was working fine, is not usually enough.
Best regards, Krzysztof