From: Taniya Das quic_tdas@quicinc.com
[ Upstream commit da94a81ea6c6f1cd2f389c5631e33c145ac7b35b ]
Update the force mem core bit for UFS AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of the UFS driver.
Signed-off-by: Taniya Das quic_tdas@quicinc.com Reviewed-by: Imran Shaik quic_imrashai@quicinc.com Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicin... Signed-off-by: Bjorn Andersson andersson@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org ---
**YES** This commit should be backported to stable kernel trees. ## Detailed Analysis: ### **Code Changes Analysis:** The commit adds a single line to each of the two affected clock drivers: ```c qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); ``` This change: 1. **Sets the FORCE_MEM_CORE_ON bit** for the UFS AXI clock in SM8650 and SM8750 platforms 2. **Forces the core-on signal to remain active** during the clock's halt state 3. **Ensures memory retention** across power state transitions 4. **Enables proper MCQ functionality** for UFS storage ### **Comparison with Similar Commits:** Looking at the historical reference commits provided, this change follows the **exact same pattern** as commits that were marked **"Backport Status: YES"**: - **Similar Commit #2 (YES)**: gcc-sc7280 setting force_mem_core for UFS ICE clock - same technical approach, same reasoning about memory retention - **Similar Commit #3 (YES)**: gcc-msm8998 disabling halt check for UFS clocks - related to UFS clock reliability - **Similar Commit #5 (YES)**: Adding missing UFS clock source - critical for UFS functionality The pattern shows that **UFS-related clock fixes are consistently backported** when they address hardware requirements or prevent data corruption. ### **Justification for Backporting:** 1. **Critical Bug Fix**: Without this change, UFS MCQ feature cannot work reliably, potentially causing data loss during power transitions 2. **Small and Contained**: The change is minimal - just one line per platform setting a hardware register bit 3. **No Side Effects**: Setting FORCE_MEM_CORE_ON is a conservative change that ensures memory retention without breaking existing functionality 4. **Hardware Requirement**: This addresses a discovered hardware requirement for MCQ functionality, not a new feature 5. **Low Regression Risk**: The change is confined to specific platforms (SM8650/SM8750) and only affects UFS clock behavior in a predictable way 6. **Data Integrity**: The commit message explicitly states this prevents loss of logic across power states, which could lead to filesystem corruption ### **Repository Analysis Confirms:** My examination of the kernel repository shows this is part of a systematic rollout of force_mem_core settings for UFS clocks across modern Qualcomm platforms. The same author (Taniya Das from Qualcomm) recently added identical changes to other platforms, indicating this is a vendor-validated hardware requirement rather than experimental code. **Conclusion**: This meets all criteria for stable backporting - it's a critical hardware enablement fix with minimal risk that prevents potential data corruption on affected UFS storage systems.
drivers/clk/qcom/gcc-sm8650.c | 2 ++ drivers/clk/qcom/gcc-sm8750.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index fa1672c4e7d81..24f98062b9dd5 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3817,7 +3817,9 @@ static int gcc_sm8650_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
+ /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52150, 0x0); diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c index b36d709760958..8092dd6b37b56 100644 --- a/drivers/clk/qcom/gcc-sm8750.c +++ b/drivers/clk/qcom/gcc-sm8750.c @@ -3244,8 +3244,9 @@ static int gcc_sm8750_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
- /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap); }