From: Masahiro Yamada
Sent: 04 June 2019 04:31
...
You could use: $(shell sh -c "command -v $(c)gcc") or maybe: $(shell command$${x:+} -v $(c)gcc)
How about this?
$(shell : ~; command -v $(c)gcc)Overcomplicated ....
I've not looked at the list of 'special characters' in make, but I suspect any variable expansion is enough. Since ${x:+} always expands to the empty string (whether or not 'x' is defined) it can't have any unfortunate side effects.
Probably, my eyes are used to Makefile. ":" is a no-op command, and it is used everywhere in kernel Makefiles in the form of "@:'
It depends on people which solution seems simpler. So, this argument tends to end up with bikesheding.
I am fully aware of ':', it is a shell builtin that always return success. Usually used when you want the side-effects of substitutions without executing anything (eg : ${foo:=bar} ), to change the result of a sequence of shell commands or as a dummy (eg while :; do :; done; ) Very annoyingly bash parses !: as something other than 'not true'.
$(shell command$${x:+} -v $(c)gcc) will be marginally faster because it is less parsing.
David
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