From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit 678d536bb454e3bbedcaa68208550ac9dc1cc066 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 8341dc04dfb3 ("iio:dac: Add support for the ad5449") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Lars-Peter Clausen lars@metafoo.de Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-47-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/dac/ad5449.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/dac/ad5449.c b/drivers/iio/dac/ad5449.c index bad9bdaafa94..4572d6f49275 100644 --- a/drivers/iio/dac/ad5449.c +++ b/drivers/iio/dac/ad5449.c @@ -68,10 +68,10 @@ struct ad5449 { uint16_t dac_cache[AD5449_MAX_CHANNELS];
/* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - __be16 data[2] ____cacheline_aligned; + __be16 data[2] __aligned(IIO_DMA_MINALIGN); };
enum ad5449_type {