From: Tharun Kumar P tharunkumar.pasumarthi@microchip.com
[ Upstream commit 45d2af82e0e6f662d0d0db20993b35cb1d8da646 ]
Hardware does not have support to disable individual chip select lines. Disable all chip select lines by using SPI_FORCE_CE bit.
Fixes: 1cc0cbea7167 ("spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch") Signed-off-by: Tharun Kumar P tharunkumar.pasumarthi@microchip.com Link: https://lore.kernel.org/r/20230404171613.1336093-4-tharunkumar.pasumarthi@mi... Signed-off-by: Mark Brown broonie@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/spi/spi-pci1xxxx.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-)
--- a/drivers/spi/spi-pci1xxxx.c +++ b/drivers/spi/spi-pci1xxxx.c @@ -114,17 +114,14 @@ static void pci1xxxx_spi_set_cs(struct s
/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */ regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); - if (enable) { + if (!enable) { + regval |= SPI_FORCE_CE; regval &= ~SPI_MST_CTL_DEVSEL_MASK; regval |= (spi->chip_select << 25); - writel(regval, - par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); } else { - regval &= ~(spi->chip_select << 25); - writel(regval, - par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); - + regval &= ~SPI_FORCE_CE; } + writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); }
static u8 pci1xxxx_get_clock_div(u32 hz) @@ -199,7 +196,7 @@ static int pci1xxxx_spi_transfer_one(str else regval &= ~SPI_MST_CTL_MODE_SEL;
- regval |= ((clkdiv << 5) | SPI_FORCE_CE); + regval |= (clkdiv << 5); regval &= ~SPI_MST_CTL_CMD_LEN_MASK; regval |= (len << 8); writel(regval, par->reg_base + @@ -223,10 +220,6 @@ static int pci1xxxx_spi_transfer_one(str } } } - - regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); - regval &= ~SPI_FORCE_CE; - writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); p->spi_xfer_in_progress = false;
return 0;