On Tue, Sep 16, 2025 at 09:58:14AM +0800, Baolu Lu wrote:
On 9/15/25 19:30, Joel Granados wrote:
On Mon, Sep 15, 2025 at 02:29:46PM +0800, Lu Baolu wrote:
The specification, Section 7.10, "Software Steps to Drain Page Requests & Responses," requires software to submit an Invalidation Wait Descriptor (inv_wait_dsc) with the Page-request Drain (PD=1) flag set, along with the Invalidation Wait Completion Status Write flag (SW=1). It then waits for the Invalidation Wait Descriptor's completion.
However, the PD field in the Invalidation Wait Descriptor is optional, as stated in Section 6.5.2.9, "Invalidation Wait Descriptor":
"Page-request Drain (PD): Remapping hardware implementations reporting Page-request draining as not supported (PDS = 0 in ECAP_REG) treat this field as reserved."
This implies that if the IOMMU doesn't support the PDS capability, software can't drain page requests and group responses as expected.
Do not enable PCI/PRI if the IOMMU doesn't support PDS.
After giving the spec another look, this is probably the way to go. However the PDS also mentions that DT must be set. Should we check ecap_dev_iotlb_support(iommu->ecap) as well?
It has already been checked.
Yes. In intel_iommu_probe_device. Thx for the clarification.
Best