Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on timer initialization

On 06/03/2024 18:23, Ley Foon Tan wrote:

In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.

Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com

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Applied, thanks