-----Original Message----- From: Niklas Cassel cassel@kernel.org Sent: 2024年8月8日 6:35 To: Hongxing Zhu hongxing.zhu@nxp.com Cc: tj@kernel.org; dlemoal@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com; linux-ide@vger.kernel.org; stable@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; kernel@pengutronix.de Subject: Re: [PATCH v4 4/6] ata: ahci_imx: Add 32bits DMA limit for i.MX8QM AHCI SATA
On Fri, Aug 02, 2024 at 02:30:45AM +0000, Hongxing Zhu wrote:
Does this solve your problem: diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 581704e61f28..fc86e2c8c42b 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -747,12 +747,11 @@ int ahci_platform_init_host(struct platform_device *pdev, ap->ops = &ata_dummy_port_ops; }
if (hpriv->cap & HOST_CAP_64) {rc = dma_coerce_mask_and_coherent(dev,DMA_BIT_MASK(64));
if (rc) {dev_err(dev, "Failed to enable 64-bit DMA.\n");return rc;}
rc = dma_coerce_mask_and_coherent(dev,DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ?64 :
32));
if (rc) {dev_err(dev, "DMA enable failed\n");return rc; } rc = ahci_reset_controller(host);Hi Niklas: I'm so sorry to reply late. About the 32bit DMA limitation of i.MX8QM AHCI SATA. It's seems that one "dma-ranges" property in the DT can let i.MX8QM SATA works fine in my past days tests without this commit. How about drop these driver changes, and add "dma-ranges" for i.MX8QM
SATA?
Thanks a lot for your kindly help.
Hello Richard,
did you try my suggested patch above?
If you look at dma-ranges: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdevicetre e-specification.readthedocs.io%2Fen%2Flatest%2Fchapter2-devicetree-basics.ht ml%23dma-ranges&data=05%7C02%7Chongxing.zhu%40nxp.com%7C97f87f99 37844f97dbf508dcb731345e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 %7C0%7C638586669175980044%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7 C%7C&sdata=PO0bQVUA7o47HAecOp27TKwwNiG1ydfQq4DTtgEva%2Fg%3D& reserved=0
"dma-ranges" property should be used on a bus device node (such as PCI host bridges).
It does not seem correct to add this property (describing the DMA limit of the AHCI controller, a PCI endpoint) on the PCI host bridge/controller.
This property belongs to the AHCI controller, not the upstream PCI host bridge/controller.
AHCI has a specific register to describe if the hardware can support 64-bit DMA addresses or not, so if my suggested patch works for you, it seems like a more elegant solution (which also avoids having to abuse device tree properties).
Hi Niklas: Thank you very much for your kindly reply. In i.MX8QM, both AHCI and PCIe are contained in HSIO(High Speed IO) module. The "dma-ranges" property is defined in HSIO dts node actually.
BTW, I had tried the method you mentioned before. Unfortunately, it doesn't work for i.MX8QM AHCI.
Best Regards Richard Zhu
Kind regards, Niklas