From: Douglas Anderson dianders@chromium.org
[ Upstream commit 14acf21c0d3f7b7298ffcd2e5b5db4a476ec6202 ]
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes: 7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node") Signed-off-by: Douglas Anderson dianders@chromium.org Acked-by: Linus Walleij linus.walleij@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0f... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7ff3a4504d0b1..286d59d11f2e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4349,7 +4349,7 @@ function = "qspi_data"; };
- qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio16", "gpio17"; function = "qspi_data"; };