On Mon, Feb 05, 2024 at 01:35:45PM +0000, Simon Horman wrote:
On Fri, Feb 02, 2024 at 01:37:17PM +0200, Louis Peens wrote:
From: Daniel Basilio daniel.basilio@corigine.com
The 1st and 2nd expansion BAR configuration registers are configured, when the driver starts up, in variables 'barcfg_msix_general' and 'barcfg_msix_xpb', respectively. The 'LengthSelect' field is ORed in from bit 0, which is incorrect. The 'LengthSelect' field should start from bit 27.
This has largely gone un-noticed because NFP_PCIE_BAR_PCIE2CPP_LengthSelect_32BIT happens to be 0.
Fixes: 4cb584e0ee7d ("nfp: add CPP access core") Cc: stable@vger.kernel.org # 4.11+ Signed-off-by: Daniel Basilio daniel.basilio@corigine.com Signed-off-by: Louis Peens louis.peens@corigine.com
Hi Daniel and Louis,
If I'm reading this right then this is a code-correctness issue and there is no runtime effect (because 0 is 0 regardless of shifting and masking).
You are reading this correctly yes.
If so, I'd suggest that this is net-next material. And, in turn, if so the Fixes tag should be dropped.
Thanks Simon. I was definitely flip-flopping on which tree to pick when preparing this, if not already merged I would have gladly dropped it from this net series. Thinking of it in terms of runtime effect is probably a useful angle, will try and do this more when picking a tree.