On Tue, Nov 11, 2025 at 03:43:36PM -0600, Bjorn Helgaas wrote:
On Tue, Nov 11, 2025 at 02:08:36PM +0100, Niklas Cassel wrote:
On Tue, Oct 21, 2025 at 08:05:17AM +0530, Manivannan Sadhasivam wrote:
On Fri, 17 Oct 2025 18:32:53 +0200, Niklas Cassel wrote:
The L1 substates support requires additional steps to work, namely: -Proper handling of the CLKREQ# sideband signal. (It is mostly handled by hardware, but software still needs to set the clkreq fields in the PCIE_CLIENT_POWER_CON register to match the hardware implementation.) -Program the frequency of the aux clock into the DSP_PCIE_PL_AUX_CLK_FREQ_OFF register. (During L1 substates the core_clk is turned off and the aux_clk is used instead.)
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Applied, thanks!
[1/1] PCI: dw-rockchip: Prevent advertising L1 Substates support commit: 40331c63e7901a2cc75ce6b5d24d50601efb833d
Last update in this thread was "Applied, thanks!"
and the patch was applied to pci/controller/dw-rockchip
since then it seems to have been demoted to pci/controller/dw-rockchip-pend
That was Oct 20, and we had some conversation about a more generic approach after that, so I moved it to dw-rockchip-pend while we worked that out.
I fleshed it out the generic approach and will post it soon.
Ok, thank you!
Kind regards, Niklas