From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit 51f30d63145cc84cb8a8e0ec96f9a8b73e6b5448 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: a8e7e88df9ec ("iio: adc: Add Maxim MAX11100 driver") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Acked-by: Jacopo Mondi jacopo@jmondi.org Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-25-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/adc/max11100.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c index eb1ce6a0315c..49e38dca8fe2 100644 --- a/drivers/iio/adc/max11100.c +++ b/drivers/iio/adc/max11100.c @@ -33,10 +33,10 @@ struct max11100_state { struct spi_device *spi;
/* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - u8 buffer[3] ____cacheline_aligned; + u8 buffer[3] __aligned(IIO_DMA_MINALIGN); };
static const struct iio_chan_spec max11100_channels[] = {