From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit b990cdfe7536a8da7e134d516350402981300016 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Update the comment to reflect that DMA safety 'may' require separate cachelines.
Fixes: 54e018da3141 ("iio:ad7266: Mark transfer buffer as __be16") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-10-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/adc/ad7266.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/ad7266.c b/drivers/iio/adc/ad7266.c index c17d9b5fbaf6..53c83e04dde5 100644 --- a/drivers/iio/adc/ad7266.c +++ b/drivers/iio/adc/ad7266.c @@ -37,7 +37,7 @@ struct ad7266_state { struct gpio_desc *gpios[3];
/* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * The buffer needs to be large enough to hold two samples (4 bytes) and * the naturally aligned timestamp (8 bytes). @@ -45,7 +45,7 @@ struct ad7266_state { struct { __be16 sample[2]; s64 timestamp; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); };
static int ad7266_wakeup(struct ad7266_state *st)