From: Vignesh Raghavendra vigneshr@ti.com
[ Upstream commit 6974371cab1c488a53960945cb139b20ebb5f16b ]
Per AM62x SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am625 Page 1.
Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com Signed-off-by: Nishanth Menon nm@ti.com Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index 887f31c23fef6..31b37abbb8d5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -96,7 +96,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; };