11 Apr
2019
11 Apr
'19
8:16 p.m.
Quoting Weiyi Lu (2019-03-04 21:05:40)
From: Owen Chen owen.chen@mediatek.com
- pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible.
- fmin: The pll freqency lower-bound is vary from 1GMhz to 1.5Ghz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen owen.chen@mediatek.com Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Acked-by: Sean Wang sean.wang@kernel.org
Applied to clk-next