From: Yang Yingliang yangyingliang@huawei.com
commit 73e770f085023da327dc9ffeb6cd96b0bb22d97e upstream.
Add missing iounmap() before return error from sifive_l2_init().
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang yangyingliang@huawei.com Reviewed-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: Conor Dooley conor.dooley@microchip.com [conor: ccache -> l2_cache] Signed-off-by: Conor Dooley conor.dooley@microchip.com --- drivers/soc/sifive/sifive_l2_cache.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index 59640a1d0b28..483aeaf0d405 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -212,7 +212,8 @@ static int __init sifive_l2_init(void) intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("L2CACHE: no interrupts property\n"); - return -ENODEV; + rc = -ENODEV; + goto err_unmap; }
for (i = 0; i < intr_num; i++) { @@ -220,7 +221,7 @@ static int __init sifive_l2_init(void) rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); if (rc) { pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); - return rc; + goto err_unmap; } }
@@ -233,5 +234,9 @@ static int __init sifive_l2_init(void) setup_sifive_debug(); #endif return 0; + +err_unmap: + iounmap(l2_base); + return rc; } device_initcall(sifive_l2_init);